riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-01-19	target/arm: Ensure icount is enabled when emulating INST_RETIRED	Philippe Mathieu-Daudé	1	-0/+2
2024-01-19	system/cpu-timers: Introduce ICountMode enumerator	Philippe Mathieu-Daudé	1	-1/+2
2024-01-19	target/alpha: Only build sys_helper.c on system emulation	Philippe Mathieu-Daudé	2	-5/+4
2024-01-19	target/alpha: Extract clk_helper.c from sys_helper.c	Philippe Mathieu-Daudé	3	-15/+33
2024-01-19	target/xtensa: use generic instruction breakpoint infrastructure	Max Filippov	5	-33/+47
2024-01-19	accel: Do not set CPUState::tcg_cflags in non-TCG accels	Philippe Mathieu-Daudé	2	-2/+2
2024-01-18	Merge tag 'pull-target-arm-20240118' of https://git.linaro.org/people/pmaydel...	Peter Maydell	1	-8/+6
2024-01-16	Merge tag 'hppa-fixes-8.2-pull-request' of https://github.com/hdeller/qemu-hp...	Peter Maydell	4	-24/+24
2024-01-15	target/arm: arm_pamax() no longer needs to do feature propagation	Peter Maydell	1	-8/+6
2024-01-13	target/hppa: Fix IOR and ISR on error in probe	Helge Deller	1	-5/+1
2024-01-13	target/hppa: Fix IOR and ISR on unaligned access trap	Helge Deller	1	-5/+1
2024-01-13	target/hppa: Export function hppa_set_ior_and_isr()	Helge Deller	2	-11/+13
2024-01-13	target/hppa: Avoid accessing %gr0 when raising exception	Helge Deller	1	-1/+1
2024-01-13	target/hppa: Fix PDC address translation on PA2.0 with PSW.W=0	Helge Deller	1	-2/+8
2024-01-12	Merge tag 'pull-request-2024-01-11' of https://gitlab.com/thuth/qemu into sta...	Peter Maydell	3	-8/+25
2024-01-11	Merge tag 'pull-loongarch-20240111' of https://gitlab.com/gaosong/qemu into s...	Peter Maydell	10	-70/+852
2024-01-11	target/s390x: Fix LAE setting a wrong access register	Ilya Leoshkevich	1	-1/+2
2024-01-11	target/s390x/kvm/pv: Provide some more useful information if decryption fails	Thomas Huth	2	-7/+23
2024-01-11	hw/loongarch/virt: Set iocsr address space per-board rather than percpu	Bibo Mao	4	-60/+10
2024-01-11	target/loongarch: Add loongarch kvm into meson build	Tianrui Zhao	2	-0/+2
2024-01-11	target/loongarch: Implement set vcpu intr for kvm	Tianrui Zhao	4	-1/+40
2024-01-11	target/loongarch: Restrict TCG-specific code	Tianrui Zhao	1	-9/+21
2024-01-11	target/loongarch: Implement kvm_arch_handle_exit	Tianrui Zhao	2	-1/+24
2024-01-11	target/loongarch: Implement kvm_arch_init_vcpu	Tianrui Zhao	3	-0/+27
2024-01-11	target/loongarch: Implement kvm_arch_init function	Tianrui Zhao	1	-0/+1
2024-01-11	target/loongarch: Implement kvm get/set registers	Tianrui Zhao	6	-3/+598
2024-01-11	target/loongarch: Supplement vcpu env initial when vcpu reset	Tianrui Zhao	2	-1/+3
2024-01-11	target/loongarch: Define some kvm_arch interfaces	Tianrui Zhao	1	-0/+131
2024-01-11	Merge tag 'pull-target-arm-20240111' of https://git.linaro.org/people/pmaydel...	Peter Maydell	14	-73/+663
2024-01-10	target/riscv: Ensure mideleg is set correctly on reset	Alistair Francis	1	-0/+8
2024-01-10	target/riscv: Don't adjust vscause for exceptions	Alistair Francis	1	-2/+2
2024-01-10	target/riscv: Assert that the CSR numbers will be correct	Alistair Francis	1	-1/+4
2024-01-10	target/riscv: pmp: Ignore writes when RW=01 and MML=0	Ivan Klokov	1	-1/+1
2024-01-10	target/riscv/kvm: add RVV and Vector CSR regs	Daniel Henrique Barboza	1	-0/+74
2024-01-10	target/riscv/kvm: do PR_RISCV_V_SET_CONTROL during realize()	Daniel Henrique Barboza	1	-0/+29
2024-01-10	target/riscv/kvm.c: remove group setting of KVM AIA if the machine only has 1...	Yong-Xuan Wang	1	-14/+17
2024-01-10	target/riscv: add rva22s64 cpu	Daniel Henrique Barboza	2	-0/+9
2024-01-10	target/riscv: add RVA22S64 profile	Daniel Henrique Barboza	1	-0/+32
2024-01-10	target/riscv: add 'parent' in profile description	Daniel Henrique Barboza	3	-1/+15
2024-01-10	target/riscv: add satp_mode profile support	Daniel Henrique Barboza	3	-0/+42
2024-01-10	target/riscv/cpu.c: add riscv_cpu_is_32bit()	Daniel Henrique Barboza	2	-1/+7
2024-01-10	target/riscv/cpu.c: finalize satp_mode earlier	Daniel Henrique Barboza	1	-8/+8
2024-01-10	target/riscv: add priv ver restriction to profiles	Daniel Henrique Barboza	3	-0/+34
2024-01-10	target/riscv: implement svade	Daniel Henrique Barboza	3	-0/+7
2024-01-10	target/riscv: add 'rva22u64' CPU	Daniel Henrique Barboza	3	-0/+27
2024-01-10	riscv-qmp-cmds.c: add profile flags in cpu-model-expansion	Daniel Henrique Barboza	1	-0/+14
2024-01-10	target/riscv/tcg: validate profiles during finalize	Daniel Henrique Barboza	1	-0/+69
2024-01-10	target/riscv/tcg: honor user choice for G MISA bits	Daniel Henrique Barboza	1	-25/+48
2024-01-10	target/riscv/tcg: add hash table insert helpers	Daniel Henrique Barboza	1	-12/+16
2024-01-10	target/riscv/tcg: handle profile MISA bits	Daniel Henrique Barboza	1	-0/+21