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2022-01-04target/ppc: do not call hreg_compute_hflags() in helper_store_mmcr0()Daniel Henrique Barboza1-1/+6
2022-01-04target/ppc: Use env->pnc_cyc_cntRichard Henderson1-98/+9
2022-01-04target/ppc: Rewrite pmu_increment_insnsRichard Henderson1-29/+49
2022-01-04target/ppc: Cache per-pmc insn and cycle count settingsRichard Henderson6-20/+58
2022-01-04target/ppc: powerpc_excp: Stop passing excp_model aroundFabiano Rosas1-22/+21
2022-01-04target/ppc: powerpc_excp: Move system call vectored code togetherFabiano Rosas1-8/+5
2022-01-04target/ppc: powerpc_excp: Set vector earlierFabiano Rosas1-8/+8
2022-01-04target/ppc: powerpc_excp: Add excp_vectors bounds checkFabiano Rosas1-3/+4
2022-01-04target/ppc: powerpc_excp: Set alternate SRRs directlyFabiano Rosas1-15/+8
2022-01-04target/ppc: do not silence snan in xscvspdpnMatheus Ferst1-4/+1
2022-01-04ppc/ppc405: Dump specific registersCédric Le Goater1-6/+21
2022-01-04ppc/ppc405: Introduce a store helper for SPR_40x_PIDCédric Le Goater3-1/+10
2022-01-04ppc/ppc405: Restore TCR and STR write handlersCédric Le Goater6-2/+30
2022-01-04ppc/ppc405: Activate MMU logsCédric Le Goater2-139/+122
2022-01-04target/ppc: Print out literal exception names in logsCédric Le Goater1-1/+74
2022-01-04target/ppc: Remove static inlineCédric Le Goater1-6/+6
2022-01-04target/ppc: Check effective address validityCédric Le Goater2-0/+6
2022-01-04target/ppc: Improve logging in Radix MMUCédric Le Goater1-3/+52
2021-12-30target/hppa: Fix atomic_store_3 for STBYRichard Henderson1-12/+15
2021-12-23target/hppa: Fix deposit assert from trans_shrpw_immRichard Henderson1-7/+12
2021-12-20target/riscv: Enable bitmanip Zb[abcs] instructionsVineet Gupta1-4/+4
2021-12-20target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructionsFrank Chang2-6/+13
2021-12-20target/riscv: rvv-1.0: update opivv_vadc_check() commentFrank Chang1-1/+1
2021-12-20target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...Frank Chang4-8/+8
2021-12-20target/riscv: rvv-1.0: add vector unit-stride mask load/store insnsFrank Chang4-0/+67
2021-12-20target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()Frank Chang1-18/+18
2021-12-20target/riscv: rvv-1.0: add vsetivli instructionFrank Chang2-0/+29
2021-12-20target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11Frank Chang1-2/+2
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal estimate instructionFrank Chang4-0/+197
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...Frank Chang4-0/+189
2021-12-20target/riscv: gdb: support vector registers for rv64 & rv32Hsiangkai Wang3-0/+187
2021-12-20target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not validFrank Chang1-0/+22
2021-12-20target/riscv: rvv-1.0: implement vstart CSRFrank Chang5-103/+199
2021-12-20target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bitsFrank Chang3-4/+4
2021-12-20target/riscv: rvv-1.0: narrowing floating-point/integer type-convertFrank Chang4-44/+97
2021-12-20target/riscv: add "set round to odd" rounding mode helper functionFrank Chang4-0/+14
2021-12-20target/riscv: rvv-1.0: widening floating-point/integer type-convertFrank Chang4-14/+63
2021-12-20target/riscv: rvv-1.0: floating-point/integer type-convert instructionsFrank Chang2-36/+59
2021-12-20target/riscv: introduce floating-point rounding mode enumFrank Chang3-15/+24
2021-12-20target/riscv: rvv-1.0: floating-point min/max instructionsFrank Chang1-12/+12
2021-12-20target/riscv: rvv-1.0: remove integer extract instructionFrank Chang2-24/+0
2021-12-20target/riscv: rvv-1.0: remove vmford.vv and vmford.vfFrank Chang4-17/+0
2021-12-20target/riscv: rvv-1.0: remove widening saturating scaled multiply-addFrank Chang4-243/+0
2021-12-20target/riscv: rvv-1.0: single-width scaling shift instructionsFrank Chang1-2/+2
2021-12-20target/riscv: rvv-1.0: widening floating-point reduction instructionsFrank Chang1-1/+8
2021-12-20target/riscv: rvv-1.0: single-width floating-point reductionFrank Chang2-9/+15
2021-12-20target/riscv: rvv-1.0: narrowing fixed-point clip instructionsFrank Chang4-50/+50
2021-12-20target/riscv: rvv-1.0: floating-point slide instructionsFrank Chang4-45/+121
2021-12-20target/riscv: rvv-1.0: slide instructionsFrank Chang1-7/+12
2021-12-20target/riscv: rvv-1.0: mask-register logical instructionsFrank Chang2-5/+2