index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target
Age
Commit message (
Expand
)
Author
Files
Lines
2021-12-30
target/hppa: Fix atomic_store_3 for STBY
Richard Henderson
1
-12
/
+15
2021-12-23
target/hppa: Fix deposit assert from trans_shrpw_imm
Richard Henderson
1
-7
/
+12
2021-12-20
target/riscv: Enable bitmanip Zb[abcs] instructions
Vineet Gupta
1
-4
/
+4
2021-12-20
target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions
Frank Chang
2
-6
/
+13
2021-12-20
target/riscv: rvv-1.0: update opivv_vadc_check() comment
Frank Chang
1
-1
/
+1
2021-12-20
target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...
Frank Chang
4
-8
/
+8
2021-12-20
target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
Frank Chang
4
-0
/
+67
2021-12-20
target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
Frank Chang
1
-18
/
+18
2021-12-20
target/riscv: rvv-1.0: add vsetivli instruction
Frank Chang
2
-0
/
+29
2021-12-20
target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
Frank Chang
1
-2
/
+2
2021-12-20
target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
Frank Chang
4
-0
/
+197
2021-12-20
target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...
Frank Chang
4
-0
/
+189
2021-12-20
target/riscv: gdb: support vector registers for rv64 & rv32
Hsiangkai Wang
3
-0
/
+187
2021-12-20
target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid
Frank Chang
1
-0
/
+22
2021-12-20
target/riscv: rvv-1.0: implement vstart CSR
Frank Chang
5
-103
/
+199
2021-12-20
target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
Frank Chang
3
-4
/
+4
2021-12-20
target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
Frank Chang
4
-44
/
+97
2021-12-20
target/riscv: add "set round to odd" rounding mode helper function
Frank Chang
4
-0
/
+14
2021-12-20
target/riscv: rvv-1.0: widening floating-point/integer type-convert
Frank Chang
4
-14
/
+63
2021-12-20
target/riscv: rvv-1.0: floating-point/integer type-convert instructions
Frank Chang
2
-36
/
+59
2021-12-20
target/riscv: introduce floating-point rounding mode enum
Frank Chang
3
-15
/
+24
2021-12-20
target/riscv: rvv-1.0: floating-point min/max instructions
Frank Chang
1
-12
/
+12
2021-12-20
target/riscv: rvv-1.0: remove integer extract instruction
Frank Chang
2
-24
/
+0
2021-12-20
target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
Frank Chang
4
-17
/
+0
2021-12-20
target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
Frank Chang
4
-243
/
+0
2021-12-20
target/riscv: rvv-1.0: single-width scaling shift instructions
Frank Chang
1
-2
/
+2
2021-12-20
target/riscv: rvv-1.0: widening floating-point reduction instructions
Frank Chang
1
-1
/
+8
2021-12-20
target/riscv: rvv-1.0: single-width floating-point reduction
Frank Chang
2
-9
/
+15
2021-12-20
target/riscv: rvv-1.0: narrowing fixed-point clip instructions
Frank Chang
4
-50
/
+50
2021-12-20
target/riscv: rvv-1.0: floating-point slide instructions
Frank Chang
4
-45
/
+121
2021-12-20
target/riscv: rvv-1.0: slide instructions
Frank Chang
1
-7
/
+12
2021-12-20
target/riscv: rvv-1.0: mask-register logical instructions
Frank Chang
2
-5
/
+2
2021-12-20
target/riscv: rvv-1.0: floating-point compare instructions
Frank Chang
1
-9
/
+0
2021-12-20
target/riscv: rvv-1.0: integer comparison instructions
Frank Chang
2
-11
/
+2
2021-12-20
target/riscv: rvv-1.0: single-width saturating add and subtract instructions
Frank Chang
1
-1
/
+1
2021-12-20
target/riscv: rvv-1.0: widening integer multiply-add instructions
Frank Chang
1
-3
/
+3
2021-12-20
target/riscv: rvv-1.0: narrowing integer right shift instructions
Frank Chang
4
-51
/
+51
2021-12-20
target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
Frank Chang
3
-26
/
+17
2021-12-20
target/riscv: rvv-1.0: single-width bit shift instructions
Frank Chang
1
-3
/
+3
2021-12-20
target/riscv: rvv-1.0: single-width averaging add and subtract instructions
Frank Chang
4
-6
/
+102
2021-12-20
target/riscv: rvv-1.0: integer extension instructions
Frank Chang
4
-0
/
+133
2021-12-20
target/riscv: rvv-1.0: whole register move instructions
Frank Chang
2
-0
/
+29
2021-12-20
target/riscv: rvv-1.0: floating-point scalar move instructions
Frank Chang
3
-26
/
+21
2021-12-20
target/riscv: rvv-1.0: floating-point move instruction
Frank Chang
1
-2
/
+14
2021-12-20
target/riscv: rvv-1.0: integer scalar move instructions
Frank Chang
2
-9
/
+37
2021-12-20
target/riscv: rvv-1.0: register gather instructions
Frank Chang
4
-12
/
+43
2021-12-20
target/riscv: rvv-1.0: allow load element with sign-extended
Frank Chang
1
-10
/
+22
2021-12-20
target/riscv: rvv-1.0: element index instruction
Frank Chang
1
-1
/
+1
2021-12-20
target/riscv: rvv-1.0: iota instruction
Frank Chang
2
-3
/
+9
2021-12-20
target/riscv: rvv-1.0: set-X-first mask bit instructions
Frank Chang
3
-8
/
+7
[next]