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2022-05-09target/arm: Enable SCR and HCR bits for RASRichard Henderson1-0/+9
2022-05-09target/arm: Add minimal RAS registersRichard Henderson2-0/+89
2022-05-09target/arm: Enable FEAT_Debugv8p4 for -cpu maxRichard Henderson2-3/+3
2022-05-09target/arm: Enable FEAT_Debugv8p2 for -cpu maxRichard Henderson3-0/+4
2022-05-09target/arm: Use field names for manipulating EL2 and EL3 modesRichard Henderson1-9/+13
2022-05-09target/arm: Annotate arm_max_initfn with FEAT identifiersRichard Henderson2-74/+74
2022-05-09target/arm: Split out aa32_max_featuresRichard Henderson3-101/+65
2022-05-09target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu maxRichard Henderson1-0/+4
2022-05-09target/arm: Update qemu-system-arm -cpu max to cortex-a57Richard Henderson1-60/+93
2022-05-09target/arm: Move cortex impdef sysregs to cpu_tcg.cRichard Henderson3-60/+69
2022-05-09target/arm: Adjust definition of CONTEXTIDR_EL2Richard Henderson1-4/+11
2022-05-09target/arm: Merge zcr reginfoRichard Henderson1-38/+17
2022-05-09target/arm: Drop EL3 no EL2 fallbacksRichard Henderson1-145/+13
2022-05-09target/arm: Handle cpreg registration for missing ELRichard Henderson2-56/+133
2022-05-07Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson2-0/+90
2022-05-07WHPX: support for xcr0Sunil Muthuswamy2-0/+90
2022-05-06target/xtensa: implement cache test option opcodesMax Filippov1-0/+38
2022-05-06target/xtensa: add clock input to xtensa CPUMax Filippov3-3/+24
2022-05-06target/xtensa: import core lx106Simon Safar5-0/+8273
2022-05-06target/xtensa: use tcg_constant_* for remaining opcodesMax Filippov1-52/+25
2022-05-06target/xtensa: use tcg_constant_* for FPU conversion opcodesMax Filippov1-12/+6
2022-05-06target/xtensa: use tcg_constant_* for numbered special registersMax Filippov1-12/+4
2022-05-06target/xtensa: use tcg_constant_* for TLB opcodesMax Filippov1-8/+4
2022-05-06target/xtensa: use tcg_constant_* for exceptionsMax Filippov1-13/+5
2022-05-06target/xtensa: use tcg_contatnt_* for numeric literalsMax Filippov1-19/+9
2022-05-06target/xtensa: fix missing tcg_temp_free in gen_window_checkMax Filippov1-2/+2
2022-05-05target/ppc: Change MSR_* to follow POWER ISA numbering conventionVíctor Colombo1-43/+44
2022-05-05target/ppc: Add unused msr bits FIELDsVíctor Colombo1-0/+25
2022-05-05target/ppc: Remove msr_de macroVíctor Colombo2-4/+3
2022-05-05target/ppc: Remove msr_hv macroVíctor Colombo6-17/+20
2022-05-05target/ppc: Remove msr_ts macroVíctor Colombo3-4/+4
2022-05-05target/ppc: Remove msr_fe0 and msr_fe1 macrosVíctor Colombo2-14/+15
2022-05-05target/ppc: Remove msr_ep macroVíctor Colombo2-3/+3
2022-05-05target/ppc: Remove msr_dr macroVíctor Colombo3-7/+8
2022-05-05target/ppc: Remove msr_ir macroVíctor Colombo3-7/+8
2022-05-05target/ppc: Remove msr_cm macroVíctor Colombo3-3/+3
2022-05-05target/ppc: Remove msr_fp macroVíctor Colombo2-7/+13
2022-05-05target/ppc: Remove msr_gs macroVíctor Colombo3-4/+4
2022-05-05target/ppc: Remove msr_me macroVíctor Colombo2-7/+7
2022-05-05target/ppc: Remove msr_pow macroVíctor Colombo3-8/+8
2022-05-05target/ppc: Remove msr_ce macroVíctor Colombo2-2/+2
2022-05-05target/ppc: Remove msr_ee macroVíctor Colombo4-8/+14
2022-05-05target/ppc: Remove msr_ile macroVíctor Colombo1-2/+2
2022-05-05target/ppc: Remove msr_ds macroVíctor Colombo2-2/+2
2022-05-05target/ppc: Remove msr_le macroVíctor Colombo4-11/+11
2022-05-05target/ppc: Remove msr_pr macroVíctor Colombo6-21/+28
2022-05-05target/ppc: Remove unused msr_* macrosVíctor Colombo1-20/+0
2022-05-05target/ppc: Remove fpscr_* macros from cpu.hVíctor Colombo3-44/+15
2022-05-05target/ppc: Fix BookE debug interrupt generationBin Meng1-2/+2
2022-05-05target/ppc: init 'rmmu_info' in kvm_get_radix_page_info()Daniel Henrique Barboza1-1/+1
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