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2022-01-28target/arm: Log CPU index in 'Taking exception' logPeter Maydell3-5/+8
In an SMP system it can be unclear which CPU is taking an exception; add the CPU index (which is the same value used in the TCG 'Trace %d:' logging) to the "Taking exception" log line to clarify it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220122182444.724087-2-peter.maydell@linaro.org
2022-01-21target/riscv: Relax UXL field for debuggingLIU Zhiwei1-4/+4
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-24-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Enable uxl field writeLIU Zhiwei2-6/+25
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-23-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Set default XLEN for hypervisorLIU Zhiwei1-0/+10
When swap regs for hypervisor, the value of vsstatus or mstatus_hs should have the right XLEN. Otherwise, it will propagate to mstatus. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-22-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Adjust scalar reg in vector with XLENLIU Zhiwei1-1/+1
When sew <= 32bits, not need to extend scalar reg. When sew > 32bits, if xlen is less that sew, we should sign extend the scalar register, except explicitly specified by the spec. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-21-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Adjust vector address with maskLIU Zhiwei1-10/+15
The mask comes from the pointer masking extension, or the max value corresponding to XLEN bits. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220120122050.41546-20-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Fix check range for first fault onlyLIU Zhiwei1-2/+2
Only check the range that has passed the address translation. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-19-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Remove VILL field in VTYPELIU Zhiwei1-1/+0
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-18-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Adjust vsetvl according to XLENLIU Zhiwei2-2/+10
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-17-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Split out the vill from vtypeLIU Zhiwei5-6/+19
We need not specially process vtype when XLEN changes. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-16-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Split pm_enabled into mask and baseLIU Zhiwei3-23/+16
Use cached cur_pmmask and cur_pmbase to infer the current PM mode. This may decrease the TCG IR by one when pm_enabled is true and pm_base_enabled is false. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-15-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Calculate address according to XLENLIU Zhiwei5-69/+21
Define one common function to compute a canonical address from a register plus offset. Merge gen_pm_adjust_address into this function. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-14-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Alloc tcg global for cur_pm[mask|base]LIU Zhiwei1-24/+8
Replace the array of pm_mask/pm_base with scalar variables. Remove the cached array value in DisasContext. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-13-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Create current pm fields in envLIU Zhiwei5-0/+68
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220120122050.41546-12-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Adjust csr write mask with XLENLIU Zhiwei2-5/+10
Write mask is representing the bits we care about. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-11-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Relax debug check for pm writeLIU Zhiwei1-0/+3
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-10-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Use gdb xml according to max mxlenLIU Zhiwei2-24/+55
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-9-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Extend pc for runtime pc writeLIU Zhiwei1-3/+19
In some cases, we must restore the guest PC to the address of the start of the TB, such as when the instruction counter hits zero. So extend pc register according to current xlen for these cases. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-8-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Ignore the pc bits above XLENLIU Zhiwei1-1/+1
The read from PC for translation is in cpu_get_tb_cpu_state, before translation. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-7-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Create xl field in envLIU Zhiwei5-32/+46
Current xlen has been used in helper functions and many other places. The computation of current xlen is not so trivial, so that we should recompute it as little as possible. Fortunately, xlen only changes in very seldom cases, such as exception, misa write, mstatus write, cpu reset, migration load. So that we can only recompute xlen in this places and cache it into CPURISCVState. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-6-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Sign extend pc for different XLENLIU Zhiwei4-9/+27
When pc is written, it is sign-extended to fill the widest supported XLEN. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-5-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Sign extend link reg for jal and jalrLIU Zhiwei2-6/+2
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-4-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Don't save pc when exception returnLIU Zhiwei3-9/+6
As pc will be written by the xepc in exception return, just ignore pc in translation. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-3-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Adjust pmpcfg access with mxlLIU Zhiwei2-8/+23
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-2-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: rvv-1.0: Allow Zve32f extension to be turned onFrank Chang1-0/+1
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-18-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insnsFrank Chang1-0/+3
Vector narrowing conversion instructions are provided to and from all supported integer EEWs for Zve32f extension. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-17-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insnsFrank Chang1-0/+18
Vector widening conversion instructions are provided to and from all supported integer EEWs for Zve32f extension. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-16-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insnsFrank Chang1-0/+1
Vector single-width floating-point reduction operations for EEW=32 are supported for Zve32f extension. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-15-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for scalar fp insnsFrank Chang1-0/+21
Zve32f extension requires the scalar processor to implement the F extension and implement all vector floating-point instructions for floating-point operands with EEW=32 (i.e., no widening floating-point operations). Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-14-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: rvv-1.0: Add Zve32f support for configuration insnsFrank Chang1-2/+2
All Zve* extensions support the vector configuration instructions. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-13-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: rvv-1.0: Add Zve32f extension into RISC-VFrank Chang5-4/+7
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-12-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: rvv-1.0: Allow Zve64f extension to be turned onFrank Chang1-0/+1
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-11-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insnsFrank Chang1-3/+6
Vector narrowing conversion instructions are provided to and from all supported integer EEWs for Zve64f extension. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-10-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insnsFrank Chang1-7/+25
Vector widening conversion instructions are provided to and from all supported integer EEWs for Zve64f extension. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-9-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insnsFrank Chang1-1/+2
Vector single-width floating-point reduction operations for EEW=32 are supported for Zve64f extension. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-8-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for scalar fp insnsFrank Chang1-10/+31
Zve64f extension requires the scalar processor to implement the F extension and implement all vector floating-point instructions for floating-point operands with EEW=32 (i.e., no widening floating-point operations). Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-7-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insnsFrank Chang1-2/+25
All Zve* extensions support all vector fixed-point arithmetic instructions, except that vsmul.vv and vsmul.vx are not supported for EEW=64 in Zve64*. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-6-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insnsFrank Chang1-6/+33
All Zve* extensions support all vector integer instructions, except that the vmulh integer multiply variants that return the high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-5-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for load and store insnsFrank Chang1-4/+15
All Zve* extensions support all vector load and store instructions, except Zve64* extensions do not support EEW=64 for index values when XLEN=32. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-4-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: rvv-1.0: Add Zve64f support for configuration insnsFrank Chang1-2/+4
All Zve* extensions support the vector configuration instructions. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-3-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: rvv-1.0: Add Zve64f extension into RISC-VFrank Chang5-2/+16
Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220118014522.13613-2-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Support virtual time context synchronizationYifei Jiang1-0/+30
Add virtual time context description to vmstate_kvmtimer. After cpu being loaded, virtual time context is updated to KVM. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Mingwang Li <limingwang@huawei.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220112081329.1835-13-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Implement virtual time adjusting with vm state changingYifei Jiang1-0/+15
We hope that virtual time adjusts with vm state changing. When a vm is stopped, guest virtual time should stop counting and kvm_timer should be stopped. When the vm is resumed, guest virtual time should continue to count and kvm_timer should be restored. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Mingwang Li <limingwang@huawei.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220112081329.1835-12-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Add kvm_riscv_get/put_regs_timerYifei Jiang2-0/+79
Add kvm_riscv_get/put_regs_timer to synchronize virtual time context from KVM. To set register of RISCV_TIMER_REG(state) will occur a error from KVM on kvm_timer_state == 0. It's better to adapt in KVM, but it doesn't matter that adaping in QEMU. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Mingwang Li <limingwang@huawei.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220112081329.1835-11-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Add host cpu typeYifei Jiang2-0/+16
'host' type cpu is set isa to RV32 or RV64 simply, more isa info will obtain from KVM in kvm_arch_init_vcpu() Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Mingwang Li <limingwang@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Message-id: 20220112081329.1835-10-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Handle KVM_EXIT_RISCV_SBI exitYifei Jiang2-1/+113
Use char-fe to handle console sbi call, which implement early console io while apply 'earlycon=sbi' into kernel parameters. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Mingwang Li <limingwang@huawei.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220112081329.1835-9-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Support setting external interrupt by KVMYifei Jiang4-1/+28
When KVM is enabled, set the S-mode external interrupt through kvm_riscv_set_irq function. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Mingwang Li <limingwang@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Message-id: 20220112081329.1835-8-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Support start kernel directly by KVMYifei Jiang6-1/+75
Get kernel and fdt start address in virt.c, and pass them to KVM when cpu reset. Add kvm_riscv.h to place riscv specific interface. In addition, PLIC is created without M-mode PLIC contexts when KVM is enabled. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Mingwang Li <limingwang@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Message-id: 20220112081329.1835-7-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Implement kvm_arch_put_registersYifei Jiang1-1/+103
Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Mingwang Li <limingwang@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Message-id: 20220112081329.1835-6-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21target/riscv: Implement kvm_arch_get_registersYifei Jiang1-1/+111
Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Mingwang Li <limingwang@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Message-id: 20220112081329.1835-5-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
generated by cgit v1.1 at 2025-02-14 08:36:54 +0000