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2021-05-16target/mips: Set set_default_nan_mode with set_snan_bit_is_oneRichard Henderson1-2/+8
2021-05-14Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20210513a'...Peter Maydell2-10/+13
2021-05-13Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2021-05-12' into ...Peter Maydell37-7613/+0
2021-05-13numa: Teach ram block notifiers about resizeable ram blocksDavid Hildenbrand2-10/+13
2021-05-12Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210...Peter Maydell29-759/+1096
2021-05-12Drop the deprecated unicore32 targetMarkus Armbruster12-3587/+0
2021-05-12Drop the deprecated lm32 targetMarkus Armbruster15-2622/+0
2021-05-12Remove the deprecated moxie targetThomas Huth12-1404/+0
2021-05-11target/riscv: Fix the RV64H decode commentAlistair Francis1-1/+1
2021-05-11target/riscv: Consolidate RV32/64 16-bit instructionsAlistair Francis5-72/+39
2021-05-11target/riscv: Consolidate RV32/64 32-bit instructionsAlistair Francis14-150/+166
2021-05-11target/riscv: Remove an unused CASE_OP_32_64 macroAlistair Francis1-6/+0
2021-05-11target/riscv: Remove the unused HSTATUS_WPRI macroAlistair Francis1-6/+0
2021-05-11target/riscv: Remove the hardcoded SATP_MODE macroAlistair Francis4-28/+56
2021-05-11target/riscv: Remove the hardcoded MSTATUS_SD macroAlistair Francis3-14/+27
2021-05-11target/riscv: Remove the hardcoded HGATP_MODE macroAlistair Francis2-20/+15
2021-05-11target/riscv: Remove the hardcoded SSTATUS_SD macroAlistair Francis2-7/+8
2021-05-11target/riscv: Remove the hardcoded RVXLEN macroAlistair Francis2-7/+5
2021-05-11target/riscv: fix a typo with interrupt namesEmmanuel Blot1-1/+1
2021-05-11target/riscv: fix exception index on instruction access faultEmmanuel Blot1-1/+3
2021-05-11target/riscv: fix vrgather macro index variable type bugFrank Chang1-2/+4
2021-05-11target/riscv: Add ePMP support for the Ibex CPUAlistair Francis1-0/+1
2021-05-11target/riscv/pmp: Remove outdated commentAlistair Francis1-4/+0
2021-05-11target/riscv: Add a config option for ePMPHou Weiying2-0/+11
2021-05-11target/riscv: Implementation of enhanced PMP (ePMP)Hou Weiying1-8/+146
2021-05-11target/riscv: Add ePMP CSR access functionsHou Weiying5-0/+76
2021-05-11target/riscv: Add the ePMP featureAlistair Francis1-0/+1
2021-05-11target/riscv: Define ePMP mseccfgHou Weiying1-0/+3
2021-05-11target/riscv: Fix the PMP is locked check when using TORAlistair Francis1-10/+16
2021-05-11target/riscv: Fixup saturate subtract functionLIU Zhiwei1-4/+4
2021-05-11riscv: don't look at SUM when accessing memory from a debugger contextJade Fink1-8/+12
2021-05-11target/riscv: Use RISCVException enum for CSR accessAlistair Francis4-36/+38
2021-05-11target/riscv: Use the RISCVException enum for CSR operationsAlistair Francis2-261/+382
2021-05-11target/riscv: Fix 32-bit HS mode access permissionsAlistair Francis1-1/+5
2021-05-11target/riscv: Use the RISCVException enum for CSR predicatesAlistair Francis2-37/+46
2021-05-11target/riscv: Convert the RISC-V exceptions to an enumAlistair Francis3-24/+26
2021-05-11target/riscv: Add Shakti C class CPUVijai Kumar K2-0/+2
2021-05-11target/riscv: Align the data type of reset vector addressDylan Jhong1-1/+1
2021-05-11target/riscv: Remove privilege v1.9 specific CSR related codeAtish Patra7-72/+23
2021-05-11target/i386: use mmu_translate for NPT walkPaolo Bonzini1-207/+36
2021-05-11target/i386: allow customizing the next phase of the translationPaolo Bonzini1-12/+18
2021-05-11target/i386: extend pg_mode to more CR0 and CR4 bitsPaolo Bonzini3-16/+39
2021-05-11target/i386: pass cr3 to mmu_translatePaolo Bonzini1-6/+6
2021-05-11target/i386: extract mmu_translatePaolo Bonzini1-65/+86
2021-05-11target/i386: move paging mode constants from SVM to cpu.hPaolo Bonzini4-21/+31
2021-05-11target/i386: merge SVM_NPTEXIT_* with PF_ERROR_* constantsPaolo Bonzini2-10/+5
2021-05-10accel: add init_accel_cpu for adapting accel behavior to CPU typeClaudio Fontana1-1/+7
2021-05-10i386: make cpu_load_efer sysemu-onlyClaudio Fontana2-15/+18
2021-05-10target/i386: gdbstub: only write CR0/CR2/CR3/EFER for sysemuClaudio Fontana1-0/+10
2021-05-10target/i386: gdbstub: introduce aux functions to read/write CS64 regsClaudio Fontana1-104/+51