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2018-03-01
arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16
Alex Bennée
3
-0
/
+69
2018-03-01
arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16
Alex Bennée
3
-0
/
+36
2018-03-01
arm/translate-a64: initial decode for simd_three_reg_same_fp16
Alex Bennée
1
-0
/
+73
2018-03-01
arm/translate-a64: handle_3same_64 comment fix
Alex Bennée
1
-2
/
+1
2018-03-01
arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
Alex Bennée
3
-54
/
+110
2018-03-01
target/arm/helper: pass explicit fpst to set_rmode
Alex Bennée
4
-22
/
+22
2018-03-01
target/arm/cpu.h: add additional float_status flags
Alex Bennée
3
-36
/
+75
2018-03-01
target/arm/cpu.h: update comment for half-precision values
Alex Bennée
1
-0
/
+1
2018-03-01
target/arm/cpu64: introduce ARM_V8_FP16 feature bit
Alex Bennée
1
-0
/
+1
2018-02-22
target/arm: Fix register definitions for VMIDR and VMPIDR
Peter Maydell
1
-4
/
+4
2018-02-21
target/*/cpu.h: remove softfloat.h
Alex Bennée
43
-26
/
+29
2018-02-19
mem: add share parameter to memory-backend-ram
Marcel Apfelbaum
1
-2
/
+2
2018-02-16
target/ppc: convert to TranslatorOps
Emilio G. Cota
1
-162
/
+167
2018-02-16
target/ppc: convert to DisasContextBase
Emilio G. Cota
3
-86
/
+91
2018-02-15
target/arm: Implement v8M MSPLIM and PSPLIM registers
Peter Maydell
3
-0
/
+69
2018-02-15
target/arm: Migrate v7m.other_sp
Peter Maydell
1
-0
/
+11
2018-02-15
target/arm: Add AIRCR to vmstate struct
Peter Maydell
1
-0
/
+4
2018-02-15
target/arm: Implement writing to CONTROL_NS for v8M
Peter Maydell
1
-0
/
+10
2018-02-15
hw/intc/armv7m_nvic: Implement SCR
Peter Maydell
2
-0
/
+19
2018-02-15
hw/intc/armv7m_nvic: Implement cache ID registers
Peter Maydell
2
-0
/
+62
2018-02-15
hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC
Peter Maydell
1
-0
/
+28
2018-02-15
target/arm: Handle SVE registers when using clear_vec_high
Richard Henderson
1
-100
/
+62
2018-02-15
target/arm: Enforce access to ZCR_EL at translation
Richard Henderson
4
-19
/
+28
2018-02-15
target/arm: Suppress TB end for FPCR/FPSR
Richard Henderson
1
-2
/
+2
2018-02-15
target/arm: Enforce FP access to FPCR/FPSR
Richard Henderson
3
-19
/
+25
2018-02-15
target/arm: Remove ARM_CP_64BIT from ZCR_EL registers
Richard Henderson
1
-4
/
+4
2018-02-14
m68k: implement movep instruction
Pavel Dovgalyuk
3
-0
/
+49
2018-02-13
hax: Support guest RAM sizes of 4GB or more
Yu Ning
8
-25
/
+88
2018-02-10
Drop unneeded system header includes
Eric Blake
2
-3
/
+0
2018-02-09
Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2018-02-07-v4' in...
Peter Maydell
28
-37
/
+25
2018-02-09
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180209'...
Peter Maydell
10
-111
/
+1302
2018-02-09
Drop superfluous includes of qapi/qmp/qjson.h
Markus Armbruster
1
-1
/
+0
2018-02-09
Include qapi/qmp/qnull.h exactly where needed
Markus Armbruster
2
-1
/
+1
2018-02-09
Include qapi/qmp/qbool.h exactly where needed
Markus Armbruster
1
-1
/
+0
2018-02-09
Include qapi/qmp/qdict.h exactly where needed
Markus Armbruster
3
-0
/
+4
2018-02-09
qdict qlist: Make most helper macros functions
Markus Armbruster
1
-0
/
+1
2018-02-09
Eliminate qapi/qmp/types.h
Markus Armbruster
1
-1
/
+0
2018-02-09
Include qapi/error.h exactly where needed
Markus Armbruster
11
-8
/
+4
2018-02-09
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20180209' into staging
Peter Maydell
16
-420
/
+563
2018-02-09
target/arm/translate.c: Fix missing 'break' for TT insns
Peter Maydell
1
-0
/
+1
2018-02-09
target/arm/kvm: gic: Prevent creating userspace GICv3 with KVM
Christoffer Dall
1
-0
/
+4
2018-02-09
target/arm: Add SVE state to TB->FLAGS
Richard Henderson
4
-1
/
+36
2018-02-09
target/arm: Add ZCR_ELx
Richard Henderson
2
-0
/
+136
2018-02-09
target/arm: Add SVE to migration state
Richard Henderson
1
-0
/
+53
2018-02-09
target/arm: Add predicate registers for SVE
Richard Henderson
1
-0
/
+12
2018-02-09
target/arm: Expand vector registers for SVE
Richard Henderson
4
-28
/
+81
2018-02-09
target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support
Ard Biesheuvel
1
-0
/
+4
2018-02-09
target/arm: implement SM4 instructions
Ard Biesheuvel
4
-0
/
+103
2018-02-09
target/arm: implement SM3 instructions
Ard Biesheuvel
4
-3
/
+186
2018-02-09
target/arm: implement SHA-3 instructions
Ard Biesheuvel
2
-4
/
+145
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