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2019-06-03i386: Enable IA32_MISC_ENABLE MWAIT bit when exposing mwait/monitorWanpeng Li2-0/+4
2019-06-01target/mips: Improve performance of certain MSA instructionsMateja Marjanovic1-109/+433
2019-06-01target/mips: Clean up lmi_helper.cAleksandar Markovic1-3/+5
2019-06-01target/mips: Clean up dsp_helper.cAleksandar Markovic1-11/+29
2019-06-01target/mips: Add emulation of MMI instruction PCPYUDMateja Marjanovic1-1/+42
2019-06-01target/mips: Add emulation of MMI instruction PCPYLDMateja Marjanovic1-1/+42
2019-06-01target/mips: Add emulation of MMI instruction PCPYHMateja Marjanovic1-1/+65
2019-05-29spapr/xive: add KVM supportCédric Le Goater2-0/+13
2019-05-29target/ppc: Use vector variable shifts for VSL, VSR, VSRARichard Henderson3-61/+12
2019-05-29target/ppc: Fix xvabs[sd]p, xvnabs[sd]p, xvneg[sd]p, xvcpsgn[sd]pAnton Blanchard1-2/+2
2019-05-29target/ppc: Optimise VSX_LOAD_SCALAR_DS and VSX_VECTOR_LOAD_STOREAnton Blanchard1-10/+58
2019-05-29target/ppc: Fix xxspltibAnton Blanchard1-4/+4
2019-05-29target/ppc: Fix vsum2swsAnton Blanchard1-1/+1
2019-05-29target/ppc: Fix vslv and vsrvAnton Blanchard1-7/+7
2019-05-29target/ppc: Fix xxbrq, xxbrwAnton Blanchard1-2/+2
2019-05-29target/ppc: Fix xvxsigdpAnton Blanchard1-1/+1
2019-05-29target/ppc/kvm: Fix trace typoBoxuan Li2-2/+2
2019-05-28Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-next-280519-2...Peter Maydell13-62/+79
2019-05-28Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-may-19-2019-v...Peter Maydell6-202/+674
2019-05-28target/mips: convert UHI_plog to use common semihosting codeAlex Bennée1-6/+6
2019-05-28target/mips: only build mips-semi for softmmuAlex Bennée3-1/+12
2019-05-28target/arm: correct return values for WRITE/READ in arm-semiAlex Bennée1-8/+12
2019-05-28target/arm: add LOG_UNIMP messages to arm-semiAlex Bennée1-2/+3
2019-05-28target/arm: use the common interface for WRITE0/WRITEC in arm-semiAlex Bennée1-25/+4
2019-05-28target/arm: fixup some of the commentary for arm-semiAlex Bennée1-9/+31
2019-05-28semihosting: move semihosting configuration into its own directoryAlex Bennée11-11/+11
2019-05-26target/mips: realign comments to fix checkpatch warningsJules Irenge1-12/+22
2019-05-26target/mips: add or remove space to fix checkpatch errorsJules Irenge1-81/+94
2019-05-26mips: Decide to map PAGE_EXEC in map_addressJakub Jermář1-5/+8
2019-05-26target/mips: Refactor and fix INSERT.<B|H|W|D> instructionsMateja Marjanovic3-18/+71
2019-05-26target/mips: Refactor and fix COPY_U.<B|H|W> instructionsMateja Marjanovic3-21/+59
2019-05-26target/mips: Refactor and fix COPY_S.<B|H|W|D> instructionsMateja Marjanovic3-21/+67
2019-05-26target/mips: Fix MSA instructions ST.<B|H|W|D> on big endian hostMateja Marjanovic1-20/+180
2019-05-26target/mips: Fix MSA instructions LD.<B|H|W|D> on big endian hostMateja Marjanovic1-20/+168
2019-05-26target/mips: Make the results of MOD_<U|S>.<B|H|W|D> the same as on hardwareMateja Marjanovic1-2/+2
2019-05-26target/mips: Make the results of DIV_<U|S>.<B|H|W|D> the same as on hardwareMateja Marjanovic1-2/+3
2019-05-24target/riscv: Only flush TLB if SATP.ASID changesJonathan Behrens1-1/+3
2019-05-24target/riscv: More accurate handling of `sip` CSRJonathan Behrens1-2/+5
2019-05-24target/riscv: Add checks for several RVC reserved operandsRichard Henderson2-3/+14
2019-05-24target/riscv: Add the HGATP register masksAlistair Francis1-0/+11
2019-05-24target/riscv: Add the HSTATUS register masksAlistair Francis1-0/+18
2019-05-24target/riscv: Add Hypervisor CSR macrosAlistair Francis1-3/+6
2019-05-24target/riscv: Allow setting mstatus virtulisation bitsAlistair Francis1-9/+8
2019-05-24target/riscv: Add the MPV and MTL mstatus bitsAlistair Francis1-3/+2
2019-05-24target/riscv: Improve the scause logicAlistair Francis1-1/+1
2019-05-24target/riscv: Trigger interrupt on MIP update asynchronouslyAlistair Francis2-8/+27
2019-05-24target/riscv: Mark privilege level 2 as reservedAlistair Francis1-1/+1
2019-05-24target/riscv: Add a base 32 and 64 bit CPUAlistair Francis2-0/+16
2019-05-24target/riscv: Create settable CPU propertiesAlistair Francis2-0/+57
2019-05-24target/riscv: Remove spaces from register namesRichard Henderson1-8/+8