riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-02-27	target/riscv: Extend the MIE CSR to support virtulisation	Alistair Francis	1	-4/+20
2020-02-27	target/riscv: Set VS bits in mideleg for Hyp extension	Alistair Francis	1	-0/+3
2020-02-27	target/riscv: Add virtual register swapping function	Alistair Francis	3	-0/+79
2020-02-27	target/riscv: Add Hypervisor machine CSRs accesses	Alistair Francis	1	-0/+27
2020-02-27	target/riscv: Add Hypervisor virtual CSRs accesses	Alistair Francis	1	-0/+116
2020-02-27	target/riscv: Add Hypervisor CSR access functions	Alistair Francis	1	-2/+134
2020-02-27	target/riscv: Dump Hypervisor registers if enabled	Alistair Francis	1	-0/+33
2020-02-27	target/riscv: Print priv and virt in disas log	Alistair Francis	1	-0/+8
2020-02-27	target/riscv: Fix CSR perm checking for HS mode	Alistair Francis	1	-4/+14
2020-02-27	target/riscv: Add the force HS exception mode	Alistair Francis	3	-0/+26
2020-02-27	target/riscv: Add the virtulisation mode	Alistair Francis	3	-0/+25
2020-02-27	target/riscv: Rename the H irqs to VS irqs	Alistair Francis	2	-9/+9
2020-02-27	target/riscv: Add support for the new execption numbers	Alistair Francis	4	-20/+37
2020-02-27	target/riscv: Add the Hypervisor CSRs to CPUState	Alistair Francis	3	-18/+48
2020-02-27	target/riscv: Add the Hypervisor extension	Alistair Francis	1	-0/+1
2020-02-27	target/riscv: Convert MIP CSR to target_ulong	Alistair Francis	2	-2/+2
2020-02-25	target/riscv: progressively load the instruction during decode	Alex Bennée	2	-23/+25
2020-02-25	Merge branch 'exec_rw_const_v4' of https://github.com/philmd/qemu into HEAD	Paolo Bonzini	7	-19/+18
2020-02-25	target/i386: check for empty register in FXAM	Paolo Bonzini	1	-1/+5
2020-02-21	target/arm: Set MVFR0.FPSP for ARMv5 cpus	Richard Henderson	1	-4/+6
2020-02-21	target/arm: Use isar_feature_aa32_simd_r32 more places	Richard Henderson	3	-13/+11
2020-02-21	target/arm: Rename isar_feature_aa32_simd_r32	Richard Henderson	2	-27/+28
2020-02-21	target/arm: Convert PMULL.8 to gvec	Richard Henderson	6	-55/+95
2020-02-21	target/arm: Convert PMULL.64 to gvec	Richard Henderson	5	-72/+39
2020-02-21	target/arm: Convert PMUL.8 to gvec	Richard Henderson	5	-37/+39
2020-02-21	target/arm: Vectorize USHL and SSHL	Richard Henderson	6	-66/+389
2020-02-21	target/arm: Correctly implement ACTLR2, HACTLR2	Peter Maydell	4	-9/+33
2020-02-21	target/arm: Use FIELD_EX32 for testing 32-bit fields	Peter Maydell	1	-9/+9
2020-02-21	target/arm: Use isar_feature function for testing AA32HPD feature	Peter Maydell	2	-2/+7
2020-02-21	target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks	Peter Maydell	6	-79/+106
2020-02-21	target/arm: Correct handling of PMCR_EL0.LC bit	Peter Maydell	1	-4/+9
2020-02-21	target/arm: Correct definition of PMCRDP	Peter Maydell	1	-1/+2
2020-02-21	target/arm: Provide ARMv8.4-PMU in '-cpu max'	Peter Maydell	1	-0/+8
2020-02-21	target/arm: Implement ARMv8.4-PMU extension	Peter Maydell	2	-1/+39
2020-02-21	target/arm: Implement ARMv8.1-PMU extension	Peter Maydell	1	-2/+30
2020-02-21	target/arm: Read debug-related ID registers from KVM	Peter Maydell	3	-0/+49
2020-02-21	target/arm: Move DBGDIDR into ARMISARegisters	Peter Maydell	5	-12/+12
2020-02-21	target/arm: Stop assuming DBGDIDR always exists	Peter Maydell	4	-19/+57
2020-02-21	target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks	Peter Maydell	4	-11/+25
2020-02-21	target/arm: Define an aa32_pmu_8_1 isar feature test function	Peter Maydell	4	-21/+27
2020-02-21	target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field	Peter Maydell	1	-1/+1
2020-02-21	target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1	Peter Maydell	3	-4/+14
2020-02-21	target/arm: Factor out PMU register definitions	Peter Maydell	1	-76/+82
2020-02-21	target/arm: Define and use any_predinv isar_feature test	Peter Maydell	2	-8/+6
2020-02-21	target/arm: Add isar_feature_any_fp16 and document naming/usage conventions	Peter Maydell	2	-2/+19
2020-02-21	target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan	Peter Maydell	1	-1/+1
2020-02-21	target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers	Peter Maydell	5	-10/+19
2020-02-21	target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid	Richard Henderson	2	-34/+37
2020-02-21	target/arm: Remove ttbr1_valid check from get_phys_addr_lpae	Richard Henderson	1	-5/+1
2020-02-21	target/arm: Fix select for aa64_va_parameters_both	Richard Henderson	1	-22/+24