riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-01-04	target/m68k: fix m68k_cpu_dump_state()	Laurent Vivier	2	-4/+8
2018-01-04	target/m68k: add the Interrupt Stack Pointer	Laurent Vivier	7	-17/+190
2018-01-04	target/m68k: add andi/ori/eori to SR/CCR	Laurent Vivier	1	-7/+46
2018-01-04	target/m68k: add 680x0 "move to SR" instruction	Laurent Vivier	1	-16/+22
2018-01-04	target/m68k: move CCR/SR functions	Laurent Vivier	1	-56/+55
2018-01-04	target/m68k: implement fsave/frestore	Laurent Vivier	1	-8/+15
2018-01-04	target/m68k: add reset	Laurent Vivier	3	-0/+24
2018-01-04	target/m68k: add cpush/cinv	Laurent Vivier	1	-0/+20
2018-01-04	target/m68k: softmmu cleanup	Laurent Vivier	1	-6/+33
2018-01-04	target/m68k: add move16	Laurent Vivier	3	-1/+82
2018-01-04	target/m68k: add chk and chk2	Laurent Vivier	5	-1/+143
2018-01-04	target/m68k: manage 680x0 stack frames	Laurent Vivier	3	-7/+164
2018-01-04	target/m68k: add CPU_LOG_INT trace	Laurent Vivier	2	-2/+123
2018-01-04	target/m68k: use insn_pc to generate instruction fault address	Laurent Vivier	1	-20/+20
2018-01-04	target/m68k: fix gen_get_ccr()	Laurent Vivier	1	-1/+0
2018-01-04	target-m68k: sync CC_OP before gen_jmp_tb()	Laurent Vivier	1	-1/+2
2017-12-21	target/m68k: fix set_cc_op()	Laurent Vivier	2	-1/+2
2017-12-21	target/m68k: add monitor.c	Laurent Vivier	2	-0/+40
2017-12-21	target/m68k: remove unused variable gen_throws_exception	Laurent Vivier	1	-10/+0
2017-12-21	cpu: refactor cpu_address_space_init()	Peter Xu	2	-18/+5
2017-12-21	target/i386: Fix handling of VEX prefixes	Peter Maydell	1	-1/+1
2017-12-21	target/i386: Fix compiler warnings	Stefan Weil	1	-3/+4
2017-12-21	hyperv: make SynIC version msr constant	Roman Kagan	2	-8/+2
2017-12-21	hyperv: ensure SINTx msrs are reset properly	Roman Kagan	1	-5/+7
2017-12-21	hyperv: set partition-wide MSRs only on first vcpu	Evgeny Yakovlev	2	-9/+19
2017-12-21	x86/cpu: Enable new SSE/AVX/AVX512 cpu features	Yang Zhong	2	-3/+9
2017-12-18	target/sh4: Convert to DisasContextBase	Richard Henderson	1	-76/+78
2017-12-18	target/sh4: Do not singlestep after exceptions	Richard Henderson	1	-16/+16
2017-12-18	target/sh4: Convert to DisasJumpType	Richard Henderson	1	-35/+30
2017-12-18	target/sh4: Use cmpxchg for movco when parallel_cpus	Richard Henderson	3	-23/+64
2017-12-18	target/sh4: fix TCG leak during gusa sequence	Alex Bennée	1	-1/+1
2017-12-18	target/sh4: add missing tcg_temp_free() in _decode_opc()	Philippe Mathieu-Daudé	1	-0/+2
2017-12-18	nios2: remove duplicated includes (in code commented out)	Philippe Mathieu-Daudé	4	-5/+3
2017-12-18	i386/hax: remove duplicated include	Philippe Mathieu-Daudé	1	-1/+0
2017-12-18	i386/hax: remove duplicated includes	Philippe Mathieu-Daudé	3	-10/+1
2017-12-18	ppc: remove duplicated includes	Philippe Mathieu-Daudé	1	-3/+0
2017-12-18	misc: remove duplicated includes	Philippe Mathieu-Daudé	1	-1/+0
2017-12-18	Remove empty statements	Ladi Prosek	3	-3/+3
2017-12-15	Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20171215-v2' into sta...	Peter Maydell	21	-348/+591
2017-12-15	target/ppc: introduce the PPC_BIT() macro	Cédric Le Goater	1	-49/+56
2017-12-15	spapr/rtas: disable the decrementer interrupt when a CPU is unplugged	Cédric Le Goater	1	-3/+6
2017-12-15	pcc: define the Power-saving mode Exit Cause Enable bits in PowerPCCPUClass	Cédric Le Goater	2	-12/+12
2017-12-15	target/ppc: Use tcg_gen_lookup_and_goto_ptr	Richard Henderson	1	-15/+8
2017-12-14	s390x: change the QEMU cpu model to a stripped down z12	David Hildenbrand	4	-59/+139
2017-12-14	s390x/tcg: we already implement the Set-Program-Parameter facility	David Hildenbrand	1	-2/+3
2017-12-14	s390x/tcg: implement extract-CPU-time facility	David Hildenbrand	5	-7/+50
2017-12-14	s390x/tcg: Implement SIGNAL ADAPTER instruction	David Hildenbrand	2	-0/+9
2017-12-14	s390x/tcg: Implement STORE CHANNEL PATH STATUS	David Hildenbrand	2	-0/+8
2017-12-14	s390x/tcg: wire up SET CHANNEL MONITOR	David Hildenbrand	4	-0/+18
2017-12-14	s390x/tcg: wire up SET ADDRESS LIMIT	David Hildenbrand	4	-0/+18