aboutsummaryrefslogtreecommitdiff
path: root/target
AgeCommit message (Expand)AuthorFilesLines
2021-03-09Various spelling fixesMichael Tokarev4-4/+4
2021-03-09Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-hex-20210306' into...Peter Maydell2-2/+3
2021-03-08Merge remote-tracking branch 'remotes/philmd-gitlab/tags/renesas-20210306' in...Peter Maydell2-62/+50
2021-03-08Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...Peter Maydell1-2/+7
2021-03-08Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210308'...Peter Maydell11-101/+160
2021-03-06target/hexagon/opcodes: Add missing varargs cleanupPhilippe Mathieu-Daudé1-0/+1
2021-03-06target/hexagon: Fix shift amount check in fASHIFTL/fLSHIFTRTaylor Simpson1-2/+2
2021-03-06target/sh4: Remove unused definitionsPhilippe Mathieu-Daudé1-11/+0
2021-03-06target/sh4: Let get_physical_address() use MMUAccessType access_typePhilippe Mathieu-Daudé1-10/+10
2021-03-06target/sh4: Remove unused 'int access_type' argumentPhilippe Mathieu-Daudé1-8/+7
2021-03-06target/sh4: Replace magic value by MMUAccessType definitionsPhilippe Mathieu-Daudé1-8/+8
2021-03-06target/sh4: Fix code style for checkpatch.plPhilippe Mathieu-Daudé1-41/+41
2021-03-06KVM: x86: do not fail if software breakpoint has already been removedPaolo Bonzini1-2/+7
2021-03-05Merge remote-tracking branch 'remotes/cohuck-gitlab/tags/s390x-20210305' into...Peter Maydell4-3/+20
2021-03-05target/arm/cpu: Update coding style to make checkpatch.pl happyPhilippe Mathieu-Daudé1-4/+8
2021-03-05target/arm: Restrict v8M IDAU to TCGPhilippe Mathieu-Daudé2-7/+8
2021-03-05target/arm: Use TCF0 and TFSRE0 for unprivileged tag checksPeter Collingbourne2-5/+10
2021-03-05target/arm: Speed up aarch64 TBL/TBXRichard Henderson4-84/+56
2021-03-05target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPURebecca Cran1-0/+4
2021-03-05target/arm: Enable FEAT_SSBS for "max" AARCH64 CPURebecca Cran1-0/+5
2021-03-05target/arm: Add support for FEAT_SSBS, Speculative Store Bypass SafeRebecca Cran4-1/+69
2021-03-04target-riscv: support QMP dump-guest-memoryYifei Jiang5-0/+210
2021-03-04target/riscv: Declare csr_ops[] with a known sizeBin Meng1-1/+1
2021-03-04target/s390x/kvm: Simplify debug codePhilippe Mathieu-Daudé1-2/+1
2021-03-04css: SCHIB measurement block origin must be alignedPierre Morel1-0/+6
2021-03-04target/s390x/arch_dump: Fix warning for the name field in the PT_NOTE sectionThomas Huth1-1/+3
2021-03-04s390x/cpu_model: disallow unpack for --only-migratableChristian Borntraeger1-0/+10
2021-03-02Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...Peter Maydell3-3/+6
2021-02-25tcg/i386: rdpmc: fix the the condtionsZheng Zhan Liang1-1/+2
2021-02-25target/i386: Add bus lock debug exception supportChenyi Qiang2-1/+3
2021-02-25target/i386: update to show preferred boolean syntax for -cpuDaniel P. Berrangé1-1/+1
2021-02-22target/cris: Plug leakage of TCG temporariesStefan Sandstrom2-59/+135
2021-02-22target/cris: Let cris_mmu_translate() use MMUAccessType access_typePhilippe Mathieu-Daudé2-13/+13
2021-02-22target/cris: Use MMUAccessType enum type when possiblePhilippe Mathieu-Daudé2-9/+8
2021-02-21Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-20210221' into ...Peter Maydell7-122/+123
2021-02-21target/mips: Use GPR move functions in gen_HILO1_tx79()Philippe Mathieu-Daudé1-17/+4
2021-02-21target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpersPhilippe Mathieu-Daudé2-0/+22
2021-02-21target/mips: Rename 128-bit upper halve GPR registersPhilippe Mathieu-Daudé1-1/+3
2021-02-21target/mips: Promote 128-bit multimedia registers as global onesPhilippe Mathieu-Daudé3-27/+34
2021-02-21target/mips: Make cpu_HI/LO registers publicPhilippe Mathieu-Daudé2-1/+2
2021-02-21target/mips: Include missing "tcg/tcg.h" headerPhilippe Mathieu-Daudé1-0/+1
2021-02-21target/mips: Remove unused 'rw' argument from page_table_walk_refill()Philippe Mathieu-Daudé1-3/+3
2021-02-21target/mips: Let CPUMIPSTLBContext::map_address() take MMUAccessTypePhilippe Mathieu-Daudé2-10/+10
2021-02-21target/mips: Let get_seg*_physical_address() take MMUAccessType argPhilippe Mathieu-Daudé1-5/+6
2021-02-21target/mips: Let get_physical_address() take MMUAccessType argumentPhilippe Mathieu-Daudé1-10/+10
2021-02-21target/mips: Let raise_mmu_exception() take MMUAccessType argumentPhilippe Mathieu-Daudé1-5/+5
2021-02-21target/mips: Let cpu_mips_translate_address() take MMUAccessType argPhilippe Mathieu-Daudé2-4/+4
2021-02-21target/mips: Let do_translate_address() take MMUAccessType argumentPhilippe Mathieu-Daudé1-3/+4
2021-02-21target/mips: Replace magic value by MMU_DATA_LOAD definitionPhilippe Mathieu-Daudé2-2/+2
2021-02-21target/mips: Remove unused MMU definitionsPhilippe Mathieu-Daudé1-16/+0