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2020-02-27target/riscv: Allow enabling the Hypervisor extensionAlistair Francis2-0/+6
2020-02-27target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis4-4/+15
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis6-0/+62
2020-02-27target/riscv: Set htval and mtval2 on execptionsAlistair Francis1-0/+10
2020-02-27target/riscv: Raise the new execptions when 2nd stage translation failsAlistair Francis1-6/+18
2020-02-27target/riscv: Implement second stage MMUAlistair Francis2-19/+175
2020-02-27target/riscv: Allow specifying MMU stageAlistair Francis1-9/+28
2020-02-27target/riscv: Respect MPRV and SPRV for floating point opsAlistair Francis1-1/+15
2020-02-27target/riscv: Mark both sstatus and msstatus_hs as dirtyAlistair Francis1-0/+13
2020-02-27target/riscv: Disable guest FP support based on virtual statusAlistair Francis1-0/+3
2020-02-27target/riscv: Only set TB flags with FP status if enabledAlistair Francis1-1/+4
2020-02-27target/riscv: Remove the hret instructionAlistair Francis2-6/+0
2020-02-27target/riscv: Add hfence instructionsAlistair Francis2-9/+54
2020-02-27target/riscv: Add Hypervisor trap return supportAlistair Francis1-10/+52
2020-02-27target/riscv: Add hypvervisor trap supportAlistair Francis1-10/+59
2020-02-27target/riscv: Generate illegal instruction on WFI when V=1Alistair Francis1-2/+3
2020-02-27target/ricsv: Flush the TLB on virtulisation mode changesAlistair Francis1-0/+5
2020-02-27target/riscv: Add support for virtual interrupt settingAlistair Francis1-5/+28
2020-02-27target/riscv: Extend the SIP CSR to support virtulisationAlistair Francis1-1/+12
2020-02-27target/riscv: Extend the MIE CSR to support virtulisationAlistair Francis1-4/+20
2020-02-27target/riscv: Set VS bits in mideleg for Hyp extensionAlistair Francis1-0/+3
2020-02-27target/riscv: Add virtual register swapping functionAlistair Francis3-0/+79
2020-02-27target/riscv: Add Hypervisor machine CSRs accessesAlistair Francis1-0/+27
2020-02-27target/riscv: Add Hypervisor virtual CSRs accessesAlistair Francis1-0/+116
2020-02-27target/riscv: Add Hypervisor CSR access functionsAlistair Francis1-2/+134
2020-02-27target/riscv: Dump Hypervisor registers if enabledAlistair Francis1-0/+33
2020-02-27target/riscv: Print priv and virt in disas logAlistair Francis1-0/+8
2020-02-27target/riscv: Fix CSR perm checking for HS modeAlistair Francis1-4/+14
2020-02-27target/riscv: Add the force HS exception modeAlistair Francis3-0/+26
2020-02-27target/riscv: Add the virtulisation modeAlistair Francis3-0/+25
2020-02-27target/riscv: Rename the H irqs to VS irqsAlistair Francis2-9/+9
2020-02-27target/riscv: Add support for the new execption numbersAlistair Francis4-20/+37
2020-02-27target/riscv: Add the Hypervisor CSRs to CPUStateAlistair Francis3-18/+48
2020-02-27target/riscv: Add the Hypervisor extensionAlistair Francis1-0/+1
2020-02-27target/riscv: Convert MIP CSR to target_ulongAlistair Francis2-2/+2
2020-02-25target/riscv: progressively load the instruction during decodeAlex Bennée2-23/+25
2020-02-25Merge branch 'exec_rw_const_v4' of https://github.com/philmd/qemu into HEADPaolo Bonzini7-19/+18
2020-02-25target/i386: check for empty register in FXAMPaolo Bonzini1-1/+5
2020-02-21target/arm: Set MVFR0.FPSP for ARMv5 cpusRichard Henderson1-4/+6
2020-02-21target/arm: Use isar_feature_aa32_simd_r32 more placesRichard Henderson3-13/+11
2020-02-21target/arm: Rename isar_feature_aa32_simd_r32Richard Henderson2-27/+28
2020-02-21target/arm: Convert PMULL.8 to gvecRichard Henderson6-55/+95
2020-02-21target/arm: Convert PMULL.64 to gvecRichard Henderson5-72/+39
2020-02-21target/arm: Convert PMUL.8 to gvecRichard Henderson5-37/+39
2020-02-21target/arm: Vectorize USHL and SSHLRichard Henderson6-66/+389
2020-02-21target/arm: Correctly implement ACTLR2, HACTLR2Peter Maydell4-9/+33
2020-02-21target/arm: Use FIELD_EX32 for testing 32-bit fieldsPeter Maydell1-9/+9
2020-02-21target/arm: Use isar_feature function for testing AA32HPD featurePeter Maydell2-2/+7
2020-02-21target/arm: Test correct register in aa32_pan and aa32_ats1e1 checksPeter Maydell6-79/+106
2020-02-21target/arm: Correct handling of PMCR_EL0.LC bitPeter Maydell1-4/+9
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