| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2023-05-19 | Revert "arm/kvm: add support for MTE" | Peter Maydell | 5 | -68/+4 |
| 2023-05-18 | Merge tag 'pull-hex-20230518-1' of https://github.com/quic/qemu into staging | Richard Henderson | 35 | -421/+1646 |
| 2023-05-18 | Hexagon (gdbstub): add HVX support | Taylor Simpson | 3 | -0/+76 |
| 2023-05-18 | Hexagon (gdbstub): fix p3:0 read and write via stub | Brian Cain | 1 | -0/+16 |
| 2023-05-18 | Hexagon: add core gdbstub xml data for LLDB | Matheus Tavares Bernardino | 1 | -1/+2 |
| 2023-05-18 | Hexagon (decode): look for pkts with multiple insns at the same slot | Matheus Tavares Bernardino | 1 | -3/+27 |
| 2023-05-18 | Hexagon (iclass): update J4_hintjumpr slot constraints | Matheus Tavares Bernardino | 1 | -2/+4 |
| 2023-05-18 | Hexagon: list available CPUs with `-cpu help` | Matheus Tavares Bernardino | 2 | -0/+23 |
| 2023-05-18 | Hexagon (target/hexagon/*.py): raise exception on reg parsing error | Matheus Tavares Bernardino | 6 | -63/+66 |
| 2023-05-18 | target/hexagon: fix = vs. == mishap | Paolo Bonzini | 2 | -3/+3 |
| 2023-05-18 | Hexagon (target/hexagon) Additional instructions handled by idef-parser | Taylor Simpson | 5 | -41/+71 |
| 2023-05-18 | Hexagon (target/hexagon) Move items to DisasContext | Taylor Simpson | 8 | -31/+21 |
| 2023-05-18 | Hexagon (target/hexagon) Move pkt_has_store_s1 to DisasContext | Taylor Simpson | 11 | -40/+51 |
| 2023-05-18 | Hexagon (target/hexagon) Move pred_written to DisasContext | Taylor Simpson | 6 | -12/+10 |
| 2023-05-18 | Hexagon (target/hexagon) Move new_pred_value to DisasContext | Taylor Simpson | 8 | -24/+23 |
| 2023-05-18 | Hexagon (target/hexagon) Move new_value to DisasContext | Taylor Simpson | 4 | -14/+9 |
| 2023-05-18 | Hexagon (target/hexagon) Make special new_value for USR | Taylor Simpson | 8 | -12/+27 |
| 2023-05-18 | Hexagon (target/hexagon) Add overrides for disabled idef-parser insns | Taylor Simpson | 2 | -0/+117 |
| 2023-05-18 | Hexagon (target/hexagon) Short-circuit more HVX single instruction packets | Taylor Simpson | 4 | -2/+44 |
| 2023-05-18 | Hexagon (target/hexagon) Short-circuit packet HVX writes | Taylor Simpson | 2 | -2/+50 |
| 2023-05-18 | Hexagon (target/hexagon) Short-circuit packet predicate writes | Taylor Simpson | 3 | -6/+24 |
| 2023-05-18 | Hexagon (target/hexagon) Short-circuit packet register writes | Taylor Simpson | 16 | -30/+128 |
| 2023-05-18 | Hexagon (target/hexagon) Mark registers as read during packet analysis | Taylor Simpson | 5 | -15/+97 |
| 2023-05-18 | Hexagon (target/hexagon) Don't overlap dest writes with source reads | Taylor Simpson | 1 | -16/+29 |
| 2023-05-18 | Hexagon (target/hexagon) Clean up pred_written usage | Taylor Simpson | 2 | -46/+23 |
| 2023-05-18 | Hexagon (target/hexagon) Eliminate uses of log_pred_write function | Taylor Simpson | 5 | -19/+104 |
| 2023-05-18 | Hexagon (target/hexagon) Remove log_reg_write from op_helper.[ch] | Taylor Simpson | 3 | -35/+0 |
| 2023-05-18 | Hexagon (target/hexagon) Add overrides for clr[tf]new | Taylor Simpson | 2 | -4/+16 |
| 2023-05-18 | Hexagon (target/hexagon) Add overrides for allocframe/deallocframe | Taylor Simpson | 2 | -0/+79 |
| 2023-05-18 | Hexagon (target/hexagon) Add overrides for loop setup instructions | Taylor Simpson | 2 | -0/+65 |
| 2023-05-18 | Hexagon (target/hexagon) Add DisasContext arg to gen_log_reg_write | Taylor Simpson | 6 | -12/+14 |
| 2023-05-18 | Hexagon (target/hexagon) Add v73 scalar instructions | Taylor Simpson | 4 | -1/+13 |
| 2023-05-18 | Hexagon (target/hexagon) Add v69 HVX instructions | Taylor Simpson | 4 | -0/+68 |
| 2023-05-18 | Hexagon (target/hexagon) Add v68 HVX instructions | Taylor Simpson | 3 | -3/+295 |
| 2023-05-18 | Hexagon (target/hexagon) Add v68 scalar instructions | Taylor Simpson | 6 | -6/+63 |
| 2023-05-18 | Hexagon (target/hexagon) Add support for v68/v69/v71/v73 | Taylor Simpson | 3 | -8/+18 |
| 2023-05-18 | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging | Richard Henderson | 5 | -42/+65 |
| 2023-05-18 | target/arm: Saturate L2CTLR_EL1 core count field rather than overflowing | Peter Maydell | 1 | -2/+9 |
| 2023-05-18 | target/arm: Convert ERET, ERETAA, ERETAB to decodetree | Peter Maydell | 2 | -108/+63 |
| 2023-05-18 | target/arm: Convert BRAA, BRAB, BLRAA, BLRAB to decodetree | Peter Maydell | 2 | -58/+43 |
| 2023-05-18 | target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to decodetree | Peter Maydell | 2 | -55/+84 |
| 2023-05-18 | target/arm: Convert BR, BLR, RET to decodetree | Peter Maydell | 2 | -6/+54 |
| 2023-05-18 | target/arm: Convert conditional branch insns to decodetree | Peter Maydell | 2 | -24/+8 |
| 2023-05-18 | target/arm: Convert TBZ, TBNZ to decodetree | Peter Maydell | 2 | -20/+11 |
| 2023-05-18 | target/arm: Convert CBZ, CBNZ to decodetree | Peter Maydell | 2 | -20/+11 |
| 2023-05-18 | target/arm: Convert unconditional branch immediate to decodetree | Peter Maydell | 2 | -19/+19 |
| 2023-05-18 | target/arm: Convert Extract instructions to decodetree | Peter Maydell | 2 | -63/+34 |
| 2023-05-18 | target/arm: Convert Bitfield to decodetree | Richard Henderson | 2 | -57/+88 |
| 2023-05-18 | target/arm: Convert Move wide (immediate) to decodetree | Richard Henderson | 2 | -43/+41 |
| 2023-05-18 | target/arm: Convert Logical (immediate) to decodetree | Richard Henderson | 2 | -64/+43 |
