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2021-09-01target-arm: Add support for Fujitsu A64FXShuuichirou Ishii1-0/+48
2021-09-01target/arm: Enable MVE in Cortex-M55Peter Maydell1-5/+2
2021-09-01target/arm: Implement MVE VRINT insnsPeter Maydell4-0/+93
2021-09-01target/arm: Implement MVE VCVT between single and half precisionPeter Maydell4-0/+108
2021-09-01target/arm: Implement MVE VCVT with specified rounding modePeter Maydell4-0/+105
2021-09-01target/arm: Implement MVE VCVT between fp and integerPeter Maydell2-0/+39
2021-09-01target/arm: Implement MVE VCVT between floating and fixed pointPeter Maydell4-0/+82
2021-09-01target/arm: Implement MVE fp scalar comparisonsPeter Maydell4-24/+131
2021-09-01target/arm: Implement MVE fp vector comparisonsPeter Maydell4-6/+137
2021-09-01target/arm: Implement MVE FP max/min across vectorPeter Maydell4-6/+102
2021-09-01target/arm: Implement MVE fp-with-scalar VFMA, VFMASPeter Maydell4-3/+56
2021-09-01target/arm: Implement MVE scalar fp insnsPeter Maydell4-6/+85
2021-09-01target/arm: Implement MVE VMAXNMA and VMINNMAPeter Maydell4-0/+42
2021-09-01target/arm: Implement MVE VCMUL and VCMLAPeter Maydell4-8/+139
2021-09-01target/arm: Implement MVE VFMA and VFMSPeter Maydell4-0/+48
2021-09-01target/arm: Implement MVE VCADDPeter Maydell4-1/+57
2021-09-01target/arm: Implement MVE VSUB, VMUL, VABD, VMAXNM, VMINNMPeter Maydell4-0/+42
2021-09-01target/arm: Implement MVE VADD (floating-point)Peter Maydell6-6/+76
2021-09-01target/riscv: Use {get,dest}_gpr for RVVRichard Henderson2-61/+26
2021-09-01target/riscv: Tidy trans_rvh.c.incRichard Henderson2-210/+57
2021-09-01target/riscv: Use {get,dest}_gpr for RVDRichard Henderson1-65/+60
2021-09-01target/riscv: Use {get,dest}_gpr for RVFRichard Henderson1-76/+70
2021-09-01target/riscv: Use gen_shift_imm_fn for slli_uwRichard Henderson1-13/+6
2021-09-01target/riscv: Use {get,dest}_gpr for RVARichard Henderson1-28/+19
2021-09-01target/riscv: Reorg csr instructionsRichard Henderson3-66/+132
2021-09-01target/riscv: Fix hgeie, hgeipRichard Henderson1-18/+8
2021-09-01target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operationRichard Henderson1-8/+15
2021-09-01target/riscv: Use {get, dest}_gpr for integer load/storeRichard Henderson1-18/+20
2021-09-01target/riscv: Use get_gpr in branchesRichard Henderson1-15/+10
2021-09-01target/riscv: Use extracts for sraiw and srliwRichard Henderson1-2/+12
2021-09-01target/riscv: Use DisasExtend in shift operationsRichard Henderson3-202/+125
2021-09-01target/riscv: Add DisasExtend to gen_unaryRichard Henderson2-23/+15
2021-09-01target/riscv: Move gen_* helpers for RVBRichard Henderson2-233/+234
2021-09-01target/riscv: Move gen_* helpers for RVMRichard Henderson2-127/+127
2021-09-01target/riscv: Use gen_arith for mulh and mulhuRichard Henderson1-22/+18
2021-09-01target/riscv: Remove gen_arith_div*Richard Henderson2-50/+8
2021-09-01target/riscv: Add DisasExtend to gen_arith*Richard Henderson4-90/+64
2021-09-01target/riscv: Introduce DisasExtend and new helpersRichard Henderson1-16/+81
2021-09-01target/riscv: Add DisasContext to gen_get_gpr, gen_set_gprRichard Henderson9-144/+144
2021-09-01target/riscv: Clean up division helpersRichard Henderson1-83/+91
2021-09-01target/riscv: Use tcg_constant_*Richard Henderson3-70/+34
2021-09-01target/riscv: Add User CSRs read-only checkLIU Zhiwei1-3/+5
2021-09-01target/riscv: Don't wrongly override isa versionLIU Zhiwei1-6/+8
2021-09-01target/riscv: Correct a comment in riscv_csrrw()Bin Meng1-1/+1
2021-08-27Merge remote-tracking branch 'remotes/dg-gitlab/tags/ppc-for-6.2-20210827' in...Peter Maydell13-1680/+1710
2021-08-27Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2021-08-26' into...Peter Maydell4-19/+6
2021-08-27target/ppc: fix vector registers access in gdbstub for little-endianMatheus Ferst1-25/+7
2021-08-27target/ppc: fix vextu[bhw][lr]x helpersMatheus Ferst1-28/+10
2021-08-27ppc/pnv: powerpc_excp: Do not discard HDECR exception when entering power-sav...Cédric Le Goater1-6/+0
2021-08-27ppc: Add a POWER10 DD2 CPUCédric Le Goater3-1/+7