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Author
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Lines
2023-06-26
target/microblaze: Define TCG_GUEST_DEFAULT_MO
Richard Henderson
1
-0
/
+3
2023-06-26
target: Widen pc/cs_base in cpu_get_tb_cpu_state
Anton Johansson
24
-54
/
+50
2023-06-26
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
Richard Henderson
7
-37
/
+90
2023-06-26
target/i386: implement SYSCALL/SYSRET in 32-bit emulators
Paolo Bonzini
6
-13
/
+11
2023-06-26
target/i386: implement RDPID in TCG
Paolo Bonzini
4
-13
/
+44
2023-06-26
target/i386: sysret and sysexit are privileged
Paolo Bonzini
1
-2
/
+2
2023-06-26
target/i386: AMD only supports SYSENTER/SYSEXIT in 32-bit mode
Paolo Bonzini
1
-4
/
+6
2023-06-26
target/i386: Intel only supports SYSCALL/SYSRET in long mode
Paolo Bonzini
2
-1
/
+12
2023-06-26
target/i386: TCG supports WBNOINVD
Paolo Bonzini
2
-2
/
+3
2023-06-26
target/i386: TCG supports XSAVEERPTR
Paolo Bonzini
1
-1
/
+3
2023-06-26
target/i386: do not accept RDSEED if CPUID bit absent
Paolo Bonzini
1
-0
/
+8
2023-06-26
target/i386: TCG supports RDSEED
Paolo Bonzini
1
-3
/
+2
2023-06-26
target/i386: TCG supports 3DNow! prefetch(w)
Paolo Bonzini
1
-1
/
+2
2023-06-26
target/i386: fix INVD vmexit
Paolo Bonzini
1
-1
/
+1
2023-06-25
target/ppc: Add msgsnd/p and DPDES SMT support
Nicholas Piggin
3
-11
/
+71
2023-06-25
target/ppc: Add support for SMT CTRL register
Nicholas Piggin
3
-1
/
+44
2023-06-25
target/ppc: Add initial flags and helpers for SMT support
Nicholas Piggin
3
-0
/
+36
2023-06-25
target/ppc: Fix sc instruction handling of LEV field
Nicholas Piggin
1
-1
/
+6
2023-06-25
target/ppc: Better CTRL SPR implementation
Nicholas Piggin
1
-1
/
+8
2023-06-25
target/ppc: Add ISA v3.1 LEV indication in SRR1 for system call interrupts
Nicholas Piggin
1
-0
/
+4
2023-06-25
target/ppc: Implement HEIR SPR
Nicholas Piggin
3
-1
/
+40
2023-06-25
target/ppc: Add SRR1 prefix indication to interrupt handlers
Nicholas Piggin
2
-4
/
+83
2023-06-25
target/ppc: Change partition-scope translate interface
Nicholas Piggin
1
-8
/
+16
2023-06-25
target/ppc: Fix instruction loading endianness in alignment interrupt
Nicholas Piggin
1
-1
/
+21
2023-06-25
target/ppc: Fix timer register accessors when !KVM
Cédric Le Goater
1
-0
/
+12
2023-06-25
target/ppc: gdbstub init spr gdb_id for all CPUs
Nicholas Piggin
1
-11
/
+19
2023-06-23
target/arm: Fix sve predicate store, 8 <= VQ <= 15
Richard Henderson
1
-1
/
+1
2023-06-23
target/arm: Restructure has_vfp_d32 test
Richard Henderson
1
-13
/
+15
2023-06-23
target/arm: Add cpu properties for enabling FEAT_RME
Richard Henderson
1
-0
/
+53
2023-06-23
target/arm: Implement the granule protection check
Richard Henderson
1
-17
/
+232
2023-06-23
target/arm: Implement GPC exceptions
Richard Henderson
4
-3
/
+126
2023-06-23
target/arm: Add GPC syndrome
Richard Henderson
1
-0
/
+10
2023-06-23
target/arm: Use get_phys_addr_with_struct for stage2
Richard Henderson
1
-10
/
+1
2023-06-23
target/arm: Move s1_is_el0 into S1Translate
Richard Henderson
1
-15
/
+12
2023-06-23
target/arm: Use get_phys_addr_with_struct in S1_ptw_translate
Richard Henderson
1
-28
/
+18
2023-06-23
target/arm: Handle no-execute for Realm and Root regimes
Richard Henderson
1
-6
/
+46
2023-06-23
target/arm: Handle Block and Page bits for security space
Richard Henderson
1
-16
/
+73
2023-06-23
target/arm: NSTable is RES0 for the RME EL3 regime
Richard Henderson
1
-14
/
+14
2023-06-23
target/arm: Pipe ARMSecuritySpace through ptw.c
Richard Henderson
1
-15
/
+71
2023-06-23
target/arm: Remove __attribute__((nonnull)) from ptw.c
Richard Henderson
1
-4
/
+2
2023-06-23
target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root}
Richard Henderson
2
-4
/
+29
2023-06-23
target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx
Richard Henderson
2
-13
/
+11
2023-06-23
target/arm: Introduce ARMSecuritySpace
Richard Henderson
2
-22
/
+127
2023-06-23
target/arm: Add RME cpregs
Richard Henderson
2
-0
/
+103
2023-06-23
target/arm: SCR_EL3.NS may be RES1
Richard Henderson
1
-0
/
+3
2023-06-23
target/arm: Update SCR and HCR for RME
Richard Henderson
2
-4
/
+11
2023-06-23
target/arm: Add isar_feature_aa64_rme
Richard Henderson
2
-0
/
+10
2023-06-21
target/tricore: Fix ICR.IE offset in RESTORE insn
Bastian Koppelmann
1
-1
/
+3
2023-06-21
target/tricore: Honour privilege changes on PSW write
Bastian Koppelmann
1
-1
/
+1
2023-06-21
target/tricore: Implement privilege level for all insns
Bastian Koppelmann
1
-10
/
+33
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