riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-02-21	target/arm: Set MVFR0.FPSP for ARMv5 cpus	Richard Henderson	1	-4/+6
2020-02-21	target/arm: Use isar_feature_aa32_simd_r32 more places	Richard Henderson	3	-13/+11
2020-02-21	target/arm: Rename isar_feature_aa32_simd_r32	Richard Henderson	2	-27/+28
2020-02-21	target/arm: Convert PMULL.8 to gvec	Richard Henderson	6	-55/+95
2020-02-21	target/arm: Convert PMULL.64 to gvec	Richard Henderson	5	-72/+39
2020-02-21	target/arm: Convert PMUL.8 to gvec	Richard Henderson	5	-37/+39
2020-02-21	target/arm: Vectorize USHL and SSHL	Richard Henderson	6	-66/+389
2020-02-21	target/arm: Correctly implement ACTLR2, HACTLR2	Peter Maydell	4	-9/+33
2020-02-21	target/arm: Use FIELD_EX32 for testing 32-bit fields	Peter Maydell	1	-9/+9
2020-02-21	target/arm: Use isar_feature function for testing AA32HPD feature	Peter Maydell	2	-2/+7
2020-02-21	target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks	Peter Maydell	6	-79/+106
2020-02-21	target/arm: Correct handling of PMCR_EL0.LC bit	Peter Maydell	1	-4/+9
2020-02-21	target/arm: Correct definition of PMCRDP	Peter Maydell	1	-1/+2
2020-02-21	target/arm: Provide ARMv8.4-PMU in '-cpu max'	Peter Maydell	1	-0/+8
2020-02-21	target/arm: Implement ARMv8.4-PMU extension	Peter Maydell	2	-1/+39
2020-02-21	target/arm: Implement ARMv8.1-PMU extension	Peter Maydell	1	-2/+30
2020-02-21	target/arm: Read debug-related ID registers from KVM	Peter Maydell	3	-0/+49
2020-02-21	target/arm: Move DBGDIDR into ARMISARegisters	Peter Maydell	5	-12/+12
2020-02-21	target/arm: Stop assuming DBGDIDR always exists	Peter Maydell	4	-19/+57
2020-02-21	target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks	Peter Maydell	4	-11/+25
2020-02-21	target/arm: Define an aa32_pmu_8_1 isar feature test function	Peter Maydell	4	-21/+27
2020-02-21	target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field	Peter Maydell	1	-1/+1
2020-02-21	target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1	Peter Maydell	3	-4/+14
2020-02-21	target/arm: Factor out PMU register definitions	Peter Maydell	1	-76/+82
2020-02-21	target/arm: Define and use any_predinv isar_feature test	Peter Maydell	2	-8/+6
2020-02-21	target/arm: Add isar_feature_any_fp16 and document naming/usage conventions	Peter Maydell	2	-2/+19
2020-02-21	target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan	Peter Maydell	1	-1/+1
2020-02-21	target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers	Peter Maydell	5	-10/+19
2020-02-21	target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid	Richard Henderson	2	-34/+37
2020-02-21	target/arm: Remove ttbr1_valid check from get_phys_addr_lpae	Richard Henderson	1	-5/+1
2020-02-21	target/arm: Fix select for aa64_va_parameters_both	Richard Henderson	1	-22/+24
2020-02-21	target/arm: Use bit 55 explicitly for pauth	Richard Henderson	1	-1/+2
2020-02-21	target/arm: Flush high bits of sve register after AdvSIMD INS	Richard Henderson	1	-0/+6
2020-02-21	target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN	Richard Henderson	1	-0/+1
2020-02-21	target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX	Richard Henderson	1	-0/+1
2020-02-21	target/arm: Flush high bits of sve register after AdvSIMD EXT	Richard Henderson	1	-0/+1
2020-02-21	target/ppc/cpu.h: Clean up comments in the struct CPUPPCState definition	BALATON Zoltan	1	-91/+54
2020-02-21	target/ppc/cpu.h: Move fpu related members closer in cpu env	BALATON Zoltan	1	-5/+4
2020-02-21	target/ppc: Fix typo in comments	BALATON Zoltan	2	-5/+5
2020-02-21	target/ppc/cpu.h: Remove duplicate includes	BALATON Zoltan	1	-2/+0
2020-02-18	target/i386/whpx: Remove superfluous semicolon	Philippe Mathieu-Daudé	1	-1/+1
2020-02-14	Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf2' i...	Peter Maydell	1	-9/+11
2020-02-14	Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200213'...	Peter Maydell	11	-118/+500
2020-02-13	target/arm: Implement ARMv8.1-VMID16 extension	Peter Maydell	1	-0/+1
2020-02-13	target/arm: Enable ARMv8.2-UAO in -cpu max	Richard Henderson	1	-0/+4
2020-02-13	target/arm: Implement UAO semantics	Richard Henderson	1	-20/+21
2020-02-13	target/arm: Update MSR access to UAO	Richard Henderson	4	-0/+44
2020-02-13	target/arm: Add ID_AA64MMFR2_EL1	Richard Henderson	3	-2/+21
2020-02-13	target/arm: Enable ARMv8.2-ATS1E1 in -cpu max	Richard Henderson	2	-0/+9
2020-02-13	target/arm: Implement ATS1E1 system registers	Richard Henderson	1	-6/+50