riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-05-26	target/ppc: Implement xxm[tf]acc and xxsetaccz	Lucas Mateus Castro (alqotel)	3	-0/+45
2022-05-26	target/ppc: Implement lwsync with weaker memory ordering	Nicholas Piggin	4	-9/+19
2022-05-26	target/ppc: Fix eieio memory ordering semantics	Nicholas Piggin	1	-1/+26
2022-05-26	target/ppc: declare vmsumsh[ms] helper with call flags	Matheus Ferst	5	-7/+8
2022-05-26	target/ppc: declare vmsumuh[ms] helper with call flags	Matheus Ferst	5	-8/+28
2022-05-26	target/ppc: declare vmsum[um]bm helpers with call flags	Matheus Ferst	5	-9/+11
2022-05-26	target/ppc: introduce do_va_helper	Matheus Ferst	1	-27/+5
2022-05-26	target/ppc: declare xxextractuw and xxinsertw helpers with call flags	Matheus Ferst	5	-47/+41
2022-05-26	target/ppc: declare xvxsigsp helper with call flags	Matheus Ferst	5	-4/+23
2022-05-26	target/ppc: declare xscvspdpn helper with call flags	Matheus Ferst	5	-4/+24
2022-05-26	target/ppc: Use TCG_CALL_NO_RWG_SE in fsel helper	Matheus Ferst	5	-12/+43
2022-05-26	target/ppc: use TCG_CALL_NO_RWG in VSX helpers without env	Matheus Ferst	1	-4/+4
2022-05-26	target/ppc: use TCG_CALL_NO_RWG in BCD helpers	Matheus Ferst	1	-15/+15
2022-05-26	target/ppc: use TCG_CALL_NO_RWG in vector helpers without env	Matheus Ferst	1	-81/+81
2022-05-26	target/ppc: declare darn32/darn64 helpers with TCG_CALL_NO_RWG	Matheus Ferst	1	-2/+2
2022-05-26	target/ppc: Rename sfprf to sfifprf where it's also used as set fi flag	Víctor Colombo	1	-56/+56
2022-05-26	target/ppc: Fix FPSCR.FI changing in float_overflow_excp()	Víctor Colombo	1	-6/+7
2022-05-26	target/ppc: Fix FPSCR.FI bit being cleared when it shouldn't	Víctor Colombo	2	-58/+66
2022-05-26	target/ppc: Fix tlbie	Leandro Lupori	1	-1/+1
2022-05-25	Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging	Richard Henderson	4	-24/+82
2022-05-25	i386: Hyper-V Direct TLB flush hypercall	Vitaly Kuznetsov	4	-0/+12
2022-05-25	i386: Hyper-V Support extended GVA ranges for TLB flush hypercalls	Vitaly Kuznetsov	4	-0/+12
2022-05-25	i386: Hyper-V XMM fast hypercall input feature	Vitaly Kuznetsov	4	-1/+11
2022-05-25	i386: Hyper-V Enlightened MSR bitmap feature	Vitaly Kuznetsov	4	-0/+15
2022-05-25	i386: Use hv_build_cpuid_leaf() for HV_CPUID_NESTED_FEATURES	Vitaly Kuznetsov	2	-11/+15
2022-05-25	target/i386/kvm: Fix disabling MPX on "-cpu host" with MPX-capable host	Maciej S. Szmigiero	1	-0/+8
2022-05-24	target/riscv: add zicsr/zifencei to isa_string	Hongren (Zenithal) Zheng	1	-0/+2
2022-05-24	target/riscv: Set [m\|s]tval for both illegal and virtual instruction traps	Anup Patel	4	-5/+23
2022-05-24	target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode	Anup Patel	1	-2/+1
2022-05-24	target/riscv: Fix csr number based privilege checking	Anup Patel	1	-2/+6
2022-05-24	target/riscv: Fix typo of mimpid cpu option	Frank Chang	3	-7/+7
2022-05-24	target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize	Weiwei Li	1	-12/+12
2022-05-24	target/riscv: Move/refactor ISA extension checks	Tsukasa OI	1	-15/+16
2022-05-24	target/riscv: FP extension requirements	Tsukasa OI	1	-0/+25
2022-05-24	target/riscv: Change "G" expansion	Tsukasa OI	1	-2/+5
2022-05-24	target/riscv: Disable "G" by default	Tsukasa OI	1	-1/+1
2022-05-24	target/riscv: Fix coding style on "G" expansion	Tsukasa OI	1	-2/+2
2022-05-24	target/riscv: Add short-isa-string option	Tsukasa OI	2	-1/+7
2022-05-24	target/riscv: Move Zhinx* extensions on ISA string	Tsukasa OI	1	-2/+2
2022-05-24	target/riscv: rvv: Fix early exit condition for whole register load/store	eopXD	1	-27/+31
2022-05-24	target/riscv: Fix VS mode hypervisor CSR access	Dylan Reid	1	-5/+5
2022-05-23	target/i386: Remove LBREn bit check when access Arch LBR MSRs	Yang Weijiang	1	-12/+9
2022-05-19	target/arm: Use FIELD definitions for CPACR, CPTR_ELx	Richard Henderson	3	-35/+74
2022-05-19	target/arm: Enable FEAT_HCX for -cpu max	Richard Henderson	3	-0/+71
2022-05-19	target/arm: Fix PAuth keys access checks for disabled SEL2	Florian Lugou	1	-1/+1
2022-05-19	target/arm: Make number of counters in PMCR follow the CPU	Peter Maydell	6	-12/+47
2022-05-19	target/arm/helper.c: Delete stray obsolete comment	Peter Maydell	1	-1/+0
2022-05-19	Fix aarch64 debug register names.	Chris Howard	1	-4/+12
2022-05-19	hw/intc/arm_gicv3: Use correct number of priority bits for the CPU	Peter Maydell	2	-0/+7
2022-05-19	target/arm: Drop unsupported_encoding() macro	Peter Maydell	2	-13/+4