riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-09-15	target/ppc: Use clmul_64	Richard Henderson	1	-14/+3
2023-09-15	target/s390x: Use clmul_64	Richard Henderson	1	-47/+13
2023-09-15	target/i386: Use clmul_64	Richard Henderson	1	-31/+9
2023-09-15	target/arm: Use clmul_64	Richard Henderson	1	-18/+4
2023-09-15	target/ppc: Use clmul_32* routines	Richard Henderson	1	-21/+7
2023-09-15	target/s390x: Use clmul_32* routines	Richard Henderson	1	-53/+22
2023-09-15	target/arm: Use clmul_32* routines	Richard Henderson	1	-13/+1
2023-09-15	target/ppc: Use clmul_16* routines	Richard Henderson	1	-1/+8
2023-09-15	target/s390x: Use clmul_16* routines	Richard Henderson	1	-3/+24
2023-09-15	target/arm: Use clmul_16* routines	Richard Henderson	3	-25/+2
2023-09-15	target/ppc: Use clmul_8* routines	Richard Henderson	1	-1/+13
2023-09-15	target/s390x: Use clmul_8* routines	Richard Henderson	1	-3/+29
2023-09-15	target/arm: Use clmul_8* routines	Richard Henderson	3	-57/+9
2023-09-13	Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging	Stefan Hajnoczi	1	-24/+22
2023-09-13	target/i386: Call accel-agnostic x86_cpu_get_supported_cpuid()	Philippe Mathieu-Daudé	1	-16/+16
2023-09-13	target/i386: Drop accel_uses_host_cpuid before x86_cpu_get_supported_cpuid	Philippe Mathieu-Daudé	1	-6/+4
2023-09-13	target/i386: Check kvm_hyperv_expand_features() return value	Philippe Mathieu-Daudé	1	-2/+2
2023-09-12	target/s390x: AP-passthrough for PV guests	Steffen Eiden	5	-0/+79
2023-09-12	target/s390x/kvm: Refactor AP functionalities	Steffen Eiden	1	-7/+17
2023-09-11	Merge tag 'pull-riscv-to-apply-20230911' of https://github.com/alistair23/qem...	Stefan Hajnoczi	23	-438/+2477
2023-09-11	Merge tag 'pull-target-arm-20230908' of https://git.linaro.org/people/pmaydel...	Stefan Hajnoczi	16	-124/+701
2023-09-11	target/riscv: don't read CSR in riscv_csrrw_do64	Nikita Shubin	1	-9/+15
2023-09-11	target/riscv: Align the AIA model to v1.0 ratified spec	Tommy Wu	1	-2/+5
2023-09-11	target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes	Leon Schuermann	1	-0/+4
2023-09-11	target/riscv: Allocate itrigger timers only once	Akihiko Odaki	3	-5/+21
2023-09-11	target/riscv: Use accelerated helper for AES64KS1I	Ard Biesheuvel	1	-12/+5
2023-09-11	hw/intc/riscv_aplic.c fix non-KVM --enable-debug build	Daniel Henrique Barboza	2	-0/+6
2023-09-11	riscv: zicond: make non-experimental	Vineet Gupta	1	-1/+1
2023-09-11	target/riscv: fix satp_mode_finalize() when satp_mode.supported = 0	Daniel Henrique Barboza	1	-3/+20
2023-09-11	target/riscv: Update CSR bits name for svadu extension	Weiwei Li	4	-15/+15
2023-09-11	target/riscv: Create an KVM AIA irqchip	Yong-Xuan Wang	2	-0/+190
2023-09-11	target/riscv: check the in-kernel irqchip support	Yong-Xuan Wang	1	-1/+9
2023-09-11	target/riscv: Fix zfa fleq.d and fltq.d	LIU Zhiwei	1	-2/+2
2023-09-11	target/riscv: Add Zihintntl extension ISA string to DTS	Jason Chien	2	-0/+3
2023-09-11	target/riscv: Implement WARL behaviour for mcountinhibit/mcounteren	Rob Bradford	1	-2/+9
2023-09-11	target/riscv: Add Zvksed ISA extension support	Max Chou	6	-1/+184
2023-09-11	crypto: Create sm4_subword	Max Chou	1	-8/+2
2023-09-11	target/riscv: Add Zvkg ISA extension support	Nazar Kazakov	6	-2/+114
2023-09-11	target/riscv: Add Zvksh ISA extension support	Lawrence Hunter	6	-2/+177
2023-09-11	target/riscv: Add Zvknh ISA extension support	Kiran Ostrolenk	6	-3/+390
2023-09-11	target/riscv: Add Zvkned ISA extension support	Nazar Kazakov	6	-1/+381
2023-09-11	target/riscv: Add Zvbb ISA extension support	Dickon Hood	6	-0/+397
2023-09-11	target/riscv: Refactor some of the generic vector functionality	Kiran Ostrolenk	2	-42/+46
2023-09-11	target/riscv: Refactor translation of vector-widening instruction	Dickon Hood	1	-29/+23
2023-09-11	target/riscv: Move vector translation checks	Nazar Kazakov	1	-16/+12
2023-09-11	target/riscv: Add Zvbc ISA extension support	Lawrence Hunter	8	-1/+146
2023-09-11	target/riscv: Remove redundant "cpu_vl == 0" checks	Nazar Kazakov	1	-30/+1
2023-09-11	target/riscv: Refactor vector-vector translation macro	Kiran Ostrolenk	1	-30/+32
2023-09-11	target/riscv: Refactor some of the generic vector functionality	Kiran Ostrolenk	4	-200/+265
2023-09-11	target/riscv: Use existing lookup tables for MixColumns	Ard Biesheuvel	1	-30/+4