| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2021-09-08 | target/sparc: Drop use of gen_io_end() | Peter Maydell | 1 | -15/+10 |
| 2021-09-07 | s390x/cpumodel: Add more feature to gen16 default model | Christian Borntraeger | 1 | -1/+7 |
| 2021-09-06 | hw/s390x/s390-skeys: lazy storage key enablement under TCG | David Hildenbrand | 2 | -0/+17 |
| 2021-09-06 | s390x/mmu_helper: avoid setting the storage key if nothing changed | David Hildenbrand | 1 | -4/+7 |
| 2021-09-06 | s390x/mmu_helper: move address validation into mmu_translate*() | David Hildenbrand | 4 | -29/+24 |
| 2021-09-06 | s390x/mmu_helper: fixup mmu_translate() documentation | David Hildenbrand | 1 | -1/+2 |
| 2021-09-06 | s390x/mmu_helper: no need to pass access type to mmu_translate_asce() | David Hildenbrand | 1 | -2/+2 |
| 2021-09-06 | s390x/tcg: check for addressing exceptions for RRBE, SSKE and ISKE | David Hildenbrand | 4 | -16/+35 |
| 2021-09-06 | s390x/tcg: convert real to absolute address for RRBE, SSKE and ISKE | David Hildenbrand | 1 | -0/+3 |
| 2021-09-06 | s390x/tcg: fix ignoring bit 63 when setting the storage key in SSKE | David Hildenbrand | 1 | -1/+1 |
| 2021-09-06 | s390x/tcg: wrap address for RRBE | David Hildenbrand | 1 | -3/+4 |
| 2021-09-06 | s390x/ioinst: Fix wrong MSCH alignment check on little endian | David Hildenbrand | 1 | -1/+1 |
| 2021-09-06 | s390x/tcg: fix and optimize SPX (SET PREFIX) | David Hildenbrand | 1 | -1/+14 |
| 2021-09-01 | target-arm: Add support for Fujitsu A64FX | Shuuichirou Ishii | 1 | -0/+48 |
| 2021-09-01 | target/arm: Enable MVE in Cortex-M55 | Peter Maydell | 1 | -5/+2 |
| 2021-09-01 | target/arm: Implement MVE VRINT insns | Peter Maydell | 4 | -0/+93 |
| 2021-09-01 | target/arm: Implement MVE VCVT between single and half precision | Peter Maydell | 4 | -0/+108 |
| 2021-09-01 | target/arm: Implement MVE VCVT with specified rounding mode | Peter Maydell | 4 | -0/+105 |
| 2021-09-01 | target/arm: Implement MVE VCVT between fp and integer | Peter Maydell | 2 | -0/+39 |
| 2021-09-01 | target/arm: Implement MVE VCVT between floating and fixed point | Peter Maydell | 4 | -0/+82 |
| 2021-09-01 | target/arm: Implement MVE fp scalar comparisons | Peter Maydell | 4 | -24/+131 |
| 2021-09-01 | target/arm: Implement MVE fp vector comparisons | Peter Maydell | 4 | -6/+137 |
| 2021-09-01 | target/arm: Implement MVE FP max/min across vector | Peter Maydell | 4 | -6/+102 |
| 2021-09-01 | target/arm: Implement MVE fp-with-scalar VFMA, VFMAS | Peter Maydell | 4 | -3/+56 |
| 2021-09-01 | target/arm: Implement MVE scalar fp insns | Peter Maydell | 4 | -6/+85 |
| 2021-09-01 | target/arm: Implement MVE VMAXNMA and VMINNMA | Peter Maydell | 4 | -0/+42 |
| 2021-09-01 | target/arm: Implement MVE VCMUL and VCMLA | Peter Maydell | 4 | -8/+139 |
| 2021-09-01 | target/arm: Implement MVE VFMA and VFMS | Peter Maydell | 4 | -0/+48 |
| 2021-09-01 | target/arm: Implement MVE VCADD | Peter Maydell | 4 | -1/+57 |
| 2021-09-01 | target/arm: Implement MVE VSUB, VMUL, VABD, VMAXNM, VMINNM | Peter Maydell | 4 | -0/+42 |
| 2021-09-01 | target/arm: Implement MVE VADD (floating-point) | Peter Maydell | 6 | -6/+76 |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVV | Richard Henderson | 2 | -61/+26 |
| 2021-09-01 | target/riscv: Tidy trans_rvh.c.inc | Richard Henderson | 2 | -210/+57 |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVD | Richard Henderson | 1 | -65/+60 |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVF | Richard Henderson | 1 | -76/+70 |
| 2021-09-01 | target/riscv: Use gen_shift_imm_fn for slli_uw | Richard Henderson | 1 | -13/+6 |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVA | Richard Henderson | 1 | -28/+19 |
| 2021-09-01 | target/riscv: Reorg csr instructions | Richard Henderson | 3 | -66/+132 |
| 2021-09-01 | target/riscv: Fix hgeie, hgeip | Richard Henderson | 1 | -18/+8 |
| 2021-09-01 | target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation | Richard Henderson | 1 | -8/+15 |
| 2021-09-01 | target/riscv: Use {get, dest}_gpr for integer load/store | Richard Henderson | 1 | -18/+20 |
| 2021-09-01 | target/riscv: Use get_gpr in branches | Richard Henderson | 1 | -15/+10 |
| 2021-09-01 | target/riscv: Use extracts for sraiw and srliw | Richard Henderson | 1 | -2/+12 |
| 2021-09-01 | target/riscv: Use DisasExtend in shift operations | Richard Henderson | 3 | -202/+125 |
| 2021-09-01 | target/riscv: Add DisasExtend to gen_unary | Richard Henderson | 2 | -23/+15 |
| 2021-09-01 | target/riscv: Move gen_* helpers for RVB | Richard Henderson | 2 | -233/+234 |
| 2021-09-01 | target/riscv: Move gen_* helpers for RVM | Richard Henderson | 2 | -127/+127 |
| 2021-09-01 | target/riscv: Use gen_arith for mulh and mulhu | Richard Henderson | 1 | -22/+18 |
| 2021-09-01 | target/riscv: Remove gen_arith_div* | Richard Henderson | 2 | -50/+8 |
| 2021-09-01 | target/riscv: Add DisasExtend to gen_arith* | Richard Henderson | 4 | -90/+64 |
