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2021-05-14
Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20210513a'...
Peter Maydell
2
-10
/
+13
2021-05-13
Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2021-05-12' into ...
Peter Maydell
37
-7613
/
+0
2021-05-13
numa: Teach ram block notifiers about resizeable ram blocks
David Hildenbrand
2
-10
/
+13
2021-05-12
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210...
Peter Maydell
29
-759
/
+1096
2021-05-12
Drop the deprecated unicore32 target
Markus Armbruster
12
-3587
/
+0
2021-05-12
Drop the deprecated lm32 target
Markus Armbruster
15
-2622
/
+0
2021-05-12
Remove the deprecated moxie target
Thomas Huth
12
-1404
/
+0
2021-05-11
target/riscv: Fix the RV64H decode comment
Alistair Francis
1
-1
/
+1
2021-05-11
target/riscv: Consolidate RV32/64 16-bit instructions
Alistair Francis
5
-72
/
+39
2021-05-11
target/riscv: Consolidate RV32/64 32-bit instructions
Alistair Francis
14
-150
/
+166
2021-05-11
target/riscv: Remove an unused CASE_OP_32_64 macro
Alistair Francis
1
-6
/
+0
2021-05-11
target/riscv: Remove the unused HSTATUS_WPRI macro
Alistair Francis
1
-6
/
+0
2021-05-11
target/riscv: Remove the hardcoded SATP_MODE macro
Alistair Francis
4
-28
/
+56
2021-05-11
target/riscv: Remove the hardcoded MSTATUS_SD macro
Alistair Francis
3
-14
/
+27
2021-05-11
target/riscv: Remove the hardcoded HGATP_MODE macro
Alistair Francis
2
-20
/
+15
2021-05-11
target/riscv: Remove the hardcoded SSTATUS_SD macro
Alistair Francis
2
-7
/
+8
2021-05-11
target/riscv: Remove the hardcoded RVXLEN macro
Alistair Francis
2
-7
/
+5
2021-05-11
target/riscv: fix a typo with interrupt names
Emmanuel Blot
1
-1
/
+1
2021-05-11
target/riscv: fix exception index on instruction access fault
Emmanuel Blot
1
-1
/
+3
2021-05-11
target/riscv: fix vrgather macro index variable type bug
Frank Chang
1
-2
/
+4
2021-05-11
target/riscv: Add ePMP support for the Ibex CPU
Alistair Francis
1
-0
/
+1
2021-05-11
target/riscv/pmp: Remove outdated comment
Alistair Francis
1
-4
/
+0
2021-05-11
target/riscv: Add a config option for ePMP
Hou Weiying
2
-0
/
+11
2021-05-11
target/riscv: Implementation of enhanced PMP (ePMP)
Hou Weiying
1
-8
/
+146
2021-05-11
target/riscv: Add ePMP CSR access functions
Hou Weiying
5
-0
/
+76
2021-05-11
target/riscv: Add the ePMP feature
Alistair Francis
1
-0
/
+1
2021-05-11
target/riscv: Define ePMP mseccfg
Hou Weiying
1
-0
/
+3
2021-05-11
target/riscv: Fix the PMP is locked check when using TOR
Alistair Francis
1
-10
/
+16
2021-05-11
target/riscv: Fixup saturate subtract function
LIU Zhiwei
1
-4
/
+4
2021-05-11
riscv: don't look at SUM when accessing memory from a debugger context
Jade Fink
1
-8
/
+12
2021-05-11
target/riscv: Use RISCVException enum for CSR access
Alistair Francis
4
-36
/
+38
2021-05-11
target/riscv: Use the RISCVException enum for CSR operations
Alistair Francis
2
-261
/
+382
2021-05-11
target/riscv: Fix 32-bit HS mode access permissions
Alistair Francis
1
-1
/
+5
2021-05-11
target/riscv: Use the RISCVException enum for CSR predicates
Alistair Francis
2
-37
/
+46
2021-05-11
target/riscv: Convert the RISC-V exceptions to an enum
Alistair Francis
3
-24
/
+26
2021-05-11
target/riscv: Add Shakti C class CPU
Vijai Kumar K
2
-0
/
+2
2021-05-11
target/riscv: Align the data type of reset vector address
Dylan Jhong
1
-1
/
+1
2021-05-11
target/riscv: Remove privilege v1.9 specific CSR related code
Atish Patra
7
-72
/
+23
2021-05-11
target/i386: use mmu_translate for NPT walk
Paolo Bonzini
1
-207
/
+36
2021-05-11
target/i386: allow customizing the next phase of the translation
Paolo Bonzini
1
-12
/
+18
2021-05-11
target/i386: extend pg_mode to more CR0 and CR4 bits
Paolo Bonzini
3
-16
/
+39
2021-05-11
target/i386: pass cr3 to mmu_translate
Paolo Bonzini
1
-6
/
+6
2021-05-11
target/i386: extract mmu_translate
Paolo Bonzini
1
-65
/
+86
2021-05-11
target/i386: move paging mode constants from SVM to cpu.h
Paolo Bonzini
4
-21
/
+31
2021-05-11
target/i386: merge SVM_NPTEXIT_* with PF_ERROR_* constants
Paolo Bonzini
2
-10
/
+5
2021-05-10
accel: add init_accel_cpu for adapting accel behavior to CPU type
Claudio Fontana
1
-1
/
+7
2021-05-10
i386: make cpu_load_efer sysemu-only
Claudio Fontana
2
-15
/
+18
2021-05-10
target/i386: gdbstub: only write CR0/CR2/CR3/EFER for sysemu
Claudio Fontana
1
-0
/
+10
2021-05-10
target/i386: gdbstub: introduce aux functions to read/write CS64 regs
Claudio Fontana
1
-104
/
+51
2021-05-10
i386: split off sysemu part of cpu.c
Claudio Fontana
4
-379
/
+429
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