riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-05-12	target/i386: do not consult nonexistent host leaves	Paolo Bonzini	1	-5/+36
2022-05-11	Clean up decorations and whitespace around header guards	Markus Armbruster	4	-8/+4
2022-05-11	Normalize header guard symbol definition	Markus Armbruster	17	-17/+17
2022-05-11	Clean up ill-advised or unusual header guards	Markus Armbruster	2	-4/+4
2022-05-11	Clean up header guards that don't match their file name	Markus Armbruster	12	-35/+32
2022-05-09	Merge tag 'pull-target-arm-20220509' of https://git.linaro.org/people/pmaydel...	Richard Henderson	14	-487/+933
2022-05-09	target/arm: Define neoverse-n1	Richard Henderson	1	-0/+66
2022-05-09	target/arm: Define cortex-a76	Richard Henderson	1	-0/+66
2022-05-09	target/arm: Enable FEAT_DGH for -cpu max	Richard Henderson	2	-0/+2
2022-05-09	target/arm: Enable FEAT_CSV3 for -cpu max	Richard Henderson	2	-0/+2
2022-05-09	target/arm: Enable FEAT_CSV2_2 for -cpu max	Richard Henderson	4	-2/+83
2022-05-09	target/arm: Enable FEAT_CSV2 for -cpu max	Richard Henderson	2	-0/+2
2022-05-09	target/arm: Enable FEAT_IESB for -cpu max	Richard Henderson	1	-0/+1
2022-05-09	target/arm: Enable FEAT_RAS for -cpu max	Richard Henderson	2	-0/+2
2022-05-09	target/arm: Implement ESB instruction	Richard Henderson	6	-15/+103
2022-05-09	target/arm: Implement virtual SError exceptions	Richard Henderson	5	-2/+91
2022-05-09	target/arm: Enable SCR and HCR bits for RAS	Richard Henderson	1	-0/+9
2022-05-09	target/arm: Add minimal RAS registers	Richard Henderson	2	-0/+89
2022-05-09	target/arm: Enable FEAT_Debugv8p4 for -cpu max	Richard Henderson	2	-3/+3
2022-05-09	target/arm: Enable FEAT_Debugv8p2 for -cpu max	Richard Henderson	3	-0/+4
2022-05-09	target/arm: Use field names for manipulating EL2 and EL3 modes	Richard Henderson	1	-9/+13
2022-05-09	target/arm: Annotate arm_max_initfn with FEAT identifiers	Richard Henderson	2	-74/+74
2022-05-09	target/arm: Split out aa32_max_features	Richard Henderson	3	-101/+65
2022-05-09	target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max	Richard Henderson	1	-0/+4
2022-05-09	target/arm: Update qemu-system-arm -cpu max to cortex-a57	Richard Henderson	1	-60/+93
2022-05-09	target/arm: Move cortex impdef sysregs to cpu_tcg.c	Richard Henderson	3	-60/+69
2022-05-09	target/arm: Adjust definition of CONTEXTIDR_EL2	Richard Henderson	1	-4/+11
2022-05-09	target/arm: Merge zcr reginfo	Richard Henderson	1	-38/+17
2022-05-09	target/arm: Drop EL3 no EL2 fallbacks	Richard Henderson	1	-145/+13
2022-05-09	target/arm: Handle cpreg registration for missing EL	Richard Henderson	2	-56/+133
2022-05-09	disas: Remove old libopcode ppc disassembler	Thomas Huth	1	-2/+0
2022-05-09	disas: Remove old libopcode i386 disassembler	Thomas Huth	1	-1/+0
2022-05-09	disas: Remove old libopcode arm disassembler	Thomas Huth	1	-8/+0
2022-05-07	Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging	Richard Henderson	2	-0/+90
2022-05-07	WHPX: support for xcr0	Sunil Muthuswamy	2	-0/+90
2022-05-06	target/xtensa: implement cache test option opcodes	Max Filippov	1	-0/+38
2022-05-06	target/xtensa: add clock input to xtensa CPU	Max Filippov	3	-3/+24
2022-05-06	target/xtensa: import core lx106	Simon Safar	5	-0/+8273
2022-05-06	target/xtensa: use tcg_constant_* for remaining opcodes	Max Filippov	1	-52/+25
2022-05-06	target/xtensa: use tcg_constant_* for FPU conversion opcodes	Max Filippov	1	-12/+6
2022-05-06	target/xtensa: use tcg_constant_* for numbered special registers	Max Filippov	1	-12/+4
2022-05-06	target/xtensa: use tcg_constant_* for TLB opcodes	Max Filippov	1	-8/+4
2022-05-06	target/xtensa: use tcg_constant_* for exceptions	Max Filippov	1	-13/+5
2022-05-06	target/xtensa: use tcg_contatnt_* for numeric literals	Max Filippov	1	-19/+9
2022-05-06	target/xtensa: fix missing tcg_temp_free in gen_window_check	Max Filippov	1	-2/+2
2022-05-05	target/ppc: Change MSR_* to follow POWER ISA numbering convention	Víctor Colombo	1	-43/+44
2022-05-05	target/ppc: Add unused msr bits FIELDs	Víctor Colombo	1	-0/+25
2022-05-05	target/ppc: Remove msr_de macro	Víctor Colombo	2	-4/+3
2022-05-05	target/ppc: Remove msr_hv macro	Víctor Colombo	6	-17/+20
2022-05-05	target/ppc: Remove msr_ts macro	Víctor Colombo	3	-4/+4