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3 daystarget/arm: Define new fp_status_f16_a32 and fp_status_f16_a64Peter Maydell4-0/+32
3 daystarget/arm: Remove now-unused vfp.fp_status and FPST_FPCRPeter Maydell4-16/+1
3 daystarget/arm: Use FPST_A64 in A64 decoderPeter Maydell3-90/+90
3 daystarget/arm: Use FPST_A32 in A32 decoderPeter Maydell1-27/+27
3 daystarget/arm: Use fp_status_a32 in vfp_cmp helpersPeter Maydell1-2/+2
3 daystarget/arm: Use fp_status_a32 in vjvct helperPeter Maydell1-1/+1
3 daystarget/arm: Use fp_status_a64 or fp_status_a32 in is_ebf()Peter Maydell1-1/+1
3 daystarget/arm: Use vfp.fp_status_a64 in A64-only helper functionsPeter Maydell2-5/+5
3 daystarget/arm: Define new fp_status_a32 and fp_status_a64Peter Maydell4-0/+30
3 daystarget/arm: Use uint32_t in vfp_exceptbits_from_host()Peter Maydell1-2/+2
3 daystarget/arm: Use FPSR_ constants in vfp_exceptbits_from_host()Peter Maydell1-6/+6
3 daystarget/arm: arm_reset_sve_state() should set FPSR, not FPCRPeter Maydell1-1/+1
7 daystarget/loongarch: Dump all generic CSR registersBibo Mao3-16/+53
7 daystarget/loongarch: Set unused flag with CSR registersBibo Mao3-1/+44
7 daystarget/loongarch: Add common source file for CSR registerBibo Mao4-107/+116
7 daystarget/loongarch: Add common header file for CSR registersBibo Mao2-15/+26
7 daystarget/loongarch: Add generic csr function typeBibo Mao1-10/+17
7 daystarget/loongarch: Remove static CSR function settingBibo Mao1-8/+8
7 daystarget/loongarch: Add dynamic function access with CSR registerBibo Mao3-3/+51
10 daysMerge tag 'pull-tcg-20250117' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi5-33/+19
12 daystarget/riscv: Support Supm and Sspm as part of Zjpm v1.0Alexey Baturo2-0/+25
12 daystarget/riscv: Add Smdbltrp ISA extension enable switchClément Léger2-0/+12
12 daystarget/riscv: Implement Smdbltrp behaviorClément Léger1-16/+41
12 daystarget/riscv: Implement Smdbltrp sret, mret and mnret behaviorClément Léger1-0/+12
12 daystarget/riscv: Add Smdbltrp CSRs handlingClément Léger4-0/+18
12 daystarget/riscv: Add Ssdbltrp ISA extension enable switchClément Léger1-0/+2
12 daystarget/riscv: Implement Ssdbltrp exception handlingClément Léger3-6/+39
12 daystarget/riscv: Implement Ssdbltrp sret, mret and mnret behaviorClément Léger1-1/+34
12 daystarget/riscv: Add Ssdbltrp CSRs handlingClément Léger5-12/+84
12 daystarget/riscv: Fix henvcfg potentially containing stale bitsClément Léger1-2/+8
12 daystarget/riscv: Add configuration for S[m|s]csrind, Smcdeleg/SsccfgAtish Patra1-0/+4
12 daystarget/riscv: Add implied rule for counter delegation extensionsAtish Patra1-1/+11
12 daystarget/riscv: Invoke pmu init after feature enableAtish Patra1-14/+14
12 daystarget/riscv: Add counter delegation/configuration supportKaiwen Xue1-12/+292
12 daystarget/riscv: Add select value range check for counter delegationKaiwen Xue1-1/+35
12 daystarget/riscv: Add counter delegation definitionsKaiwen Xue3-1/+9
12 daystarget/riscv: Add properties for counter delegation ISA extensionsAtish Patra2-0/+4
12 daystarget/riscv: Support generic CSR indirect accessKaiwen Xue2-6/+166
12 daystarget/riscv: Enable S*stateen bits for AIAAtish Patra1-1/+84
12 daystarget/riscv: Decouple AIA processing from xiselect and xiregKaiwen Xue1-26/+139
12 daystarget/riscv: Add properties for Indirect CSR Access extensionKaiwen Xue2-0/+4
12 daystarget/riscv: Have kvm_riscv_get_timebase_frequency() take RISCVCPU cpuPhilippe Mathieu-Daudé2-3/+5
12 daystarget/riscv: Add Zicfilp support for SmrnmiFrank Chang3-1/+20
12 daystarget/riscv: Add Smrnmi cpu extensionTommy Wu2-0/+11
12 daystarget/riscv: Add Smrnmi mnret instructionTommy Wu4-5/+64
12 daystarget/riscv: Handle Smrnmi interrupt and exceptionTommy Wu4-7/+107
12 daystarget/riscv: Add Smrnmi CSRsTommy Wu4-0/+105
12 daystarget/riscv: Add 'ext_smrnmi' in the RISCVCPUConfigTommy Wu1-0/+1
12 daystarget/riscv: Enable updates for pointer masking variables and thus enable po...Alexey Baturo1-0/+6
12 daystarget/riscv: Apply pointer masking for virtualized memory accessesAlexey Baturo5-29/+82
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