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2021-12-23target/hppa: Fix deposit assert from trans_shrpw_immRichard Henderson1-7/+12
2021-12-20target/riscv: Enable bitmanip Zb[abcs] instructionsVineet Gupta1-4/+4
2021-12-20target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructionsFrank Chang2-6/+13
2021-12-20target/riscv: rvv-1.0: update opivv_vadc_check() commentFrank Chang1-1/+1
2021-12-20target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...Frank Chang4-8/+8
2021-12-20target/riscv: rvv-1.0: add vector unit-stride mask load/store insnsFrank Chang4-0/+67
2021-12-20target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()Frank Chang1-18/+18
2021-12-20target/riscv: rvv-1.0: add vsetivli instructionFrank Chang2-0/+29
2021-12-20target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11Frank Chang1-2/+2
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal estimate instructionFrank Chang4-0/+197
2021-12-20target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...Frank Chang4-0/+189
2021-12-20target/riscv: gdb: support vector registers for rv64 & rv32Hsiangkai Wang3-0/+187
2021-12-20target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not validFrank Chang1-0/+22
2021-12-20target/riscv: rvv-1.0: implement vstart CSRFrank Chang5-103/+199
2021-12-20target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bitsFrank Chang3-4/+4
2021-12-20target/riscv: rvv-1.0: narrowing floating-point/integer type-convertFrank Chang4-44/+97
2021-12-20target/riscv: add "set round to odd" rounding mode helper functionFrank Chang4-0/+14
2021-12-20target/riscv: rvv-1.0: widening floating-point/integer type-convertFrank Chang4-14/+63
2021-12-20target/riscv: rvv-1.0: floating-point/integer type-convert instructionsFrank Chang2-36/+59
2021-12-20target/riscv: introduce floating-point rounding mode enumFrank Chang3-15/+24
2021-12-20target/riscv: rvv-1.0: floating-point min/max instructionsFrank Chang1-12/+12
2021-12-20target/riscv: rvv-1.0: remove integer extract instructionFrank Chang2-24/+0
2021-12-20target/riscv: rvv-1.0: remove vmford.vv and vmford.vfFrank Chang4-17/+0
2021-12-20target/riscv: rvv-1.0: remove widening saturating scaled multiply-addFrank Chang4-243/+0
2021-12-20target/riscv: rvv-1.0: single-width scaling shift instructionsFrank Chang1-2/+2
2021-12-20target/riscv: rvv-1.0: widening floating-point reduction instructionsFrank Chang1-1/+8
2021-12-20target/riscv: rvv-1.0: single-width floating-point reductionFrank Chang2-9/+15
2021-12-20target/riscv: rvv-1.0: narrowing fixed-point clip instructionsFrank Chang4-50/+50
2021-12-20target/riscv: rvv-1.0: floating-point slide instructionsFrank Chang4-45/+121
2021-12-20target/riscv: rvv-1.0: slide instructionsFrank Chang1-7/+12
2021-12-20target/riscv: rvv-1.0: mask-register logical instructionsFrank Chang2-5/+2
2021-12-20target/riscv: rvv-1.0: floating-point compare instructionsFrank Chang1-9/+0
2021-12-20target/riscv: rvv-1.0: integer comparison instructionsFrank Chang2-11/+2
2021-12-20target/riscv: rvv-1.0: single-width saturating add and subtract instructionsFrank Chang1-1/+1
2021-12-20target/riscv: rvv-1.0: widening integer multiply-add instructionsFrank Chang1-3/+3
2021-12-20target/riscv: rvv-1.0: narrowing integer right shift instructionsFrank Chang4-51/+51
2021-12-20target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrowFrank Chang3-26/+17
2021-12-20target/riscv: rvv-1.0: single-width bit shift instructionsFrank Chang1-3/+3
2021-12-20target/riscv: rvv-1.0: single-width averaging add and subtract instructionsFrank Chang4-6/+102
2021-12-20target/riscv: rvv-1.0: integer extension instructionsFrank Chang4-0/+133
2021-12-20target/riscv: rvv-1.0: whole register move instructionsFrank Chang2-0/+29
2021-12-20target/riscv: rvv-1.0: floating-point scalar move instructionsFrank Chang3-26/+21
2021-12-20target/riscv: rvv-1.0: floating-point move instructionFrank Chang1-2/+14
2021-12-20target/riscv: rvv-1.0: integer scalar move instructionsFrank Chang2-9/+37
2021-12-20target/riscv: rvv-1.0: register gather instructionsFrank Chang4-12/+43
2021-12-20target/riscv: rvv-1.0: allow load element with sign-extendedFrank Chang1-10/+22
2021-12-20target/riscv: rvv-1.0: element index instructionFrank Chang1-1/+1
2021-12-20target/riscv: rvv-1.0: iota instructionFrank Chang2-3/+9
2021-12-20target/riscv: rvv-1.0: set-X-first mask bit instructionsFrank Chang3-8/+7
2021-12-20target/riscv: rvv-1.0: find-first-set mask bit instructionFrank Chang4-7/+7
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