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2019-01-31Merge remote-tracking branch ↵Peter Maydell33-39/+39
'remotes/vivier2/tags/trivial-branch-pull-request' into staging - add device category (edu, i8042, sd memory card) - code clean-up - LGPL information clean-up - fix typo (acpi) # gpg: Signature made Wed 30 Jan 2019 13:21:50 GMT # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-pull-request: virtio-blk: remove duplicate definition of VirtIOBlock *s pointer hw/block: clean up stale xen_disk trace entries target/m68k: Fix LGPL information in the file headers target/s390x: Fix LGPL version in the file header comments tcg: Fix LGPL version number target/tricore: Fix LGPL version number target/openrisc: Fix LGPL version number COPYING.LIB: Synchronize the LGPL 2.1 with the version from gnu.org Don't talk about the LGPL if the file is licensed under the GPL hw: sd: set category of the sd memory card hw: input: set category of the i8042 device typo: apci->acpi hw: edu: set category of the edu device Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-30target/m68k: Fix LGPL information in the file headersThomas Huth6-10/+10
It's either "GNU *Library* General Public License version 2" or "GNU Lesser General Public License version *2.1*", but there was no "version 2.0" of the "Lesser" license. So assume that version 2.1 is meant here. Also some files mention the GPL instead of the LGPL after declaring that the files are licensed under the LGPL, so change these spots to use LGPL, too. Reviewed-by: Liam Merwick <liam.merwick@oracle.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1548769438-28942-1-git-send-email-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-01-30target/s390x: Fix LGPL version in the file header commentsThomas Huth9-9/+9
It's either "GNU *Library* General Public License version 2" or "GNU Lesser General Public License version *2.1*", but there was no "version 2.0" of the "Lesser" license. So assume that version 2.1 is meant here. Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <1548769067-20792-1-git-send-email-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-01-30target/tricore: Fix LGPL version numberThomas Huth10-10/+10
It's either "GNU *Library* General Public version 2" or "GNU Lesser General Public version *2.1*", but there was no "version 2.0" of the "Lesser" library. So assume that version 2.1 is meant here. Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1548252536-6242-4-git-send-email-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-01-30target/openrisc: Fix LGPL version numberThomas Huth7-7/+7
It's either "GNU *Library* General Public version 2" or "GNU Lesser General Public version *2.1*", but there was no "version 2.0" of the "Lesser" library. So assume that version 2.1 is meant here. Cc: Stafford Horne <shorne@gmail.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1548252536-6242-3-git-send-email-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-01-30Don't talk about the LGPL if the file is licensed under the GPLThomas Huth1-3/+3
Some files claim that the code is licensed under the GPL, but then suddenly suggest that the user should have a look at the LGPL. That's of course non-sense, replace it with the correct GPL wording instead. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1548255083-8190-1-git-send-email-thuth@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-01-29Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' ↵Peter Maydell1-1/+9
into staging x86 queue, 2019-01-28 Two small CPU model updates: * Enable NPT and NRIPSAVE on AMD CPUs * Update stepping of Cascadelake-Server # gpg: Signature made Mon 28 Jan 2019 19:36:52 GMT # gpg: using RSA key 2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-next-pull-request: i386: Enable NPT and NRIPSAVE for AMD CPUs i386: Update stepping of Cascadelake-Server Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-29target/arm: Don't clear supported PMU events when initializing PMCEID1Aaron Lindsay OS3-19/+22
A bug was introduced during a respin of: commit 57a4a11b2b281bb548b419ca81bfafb214e4c77a target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0 This patch introduced two calls to get_pmceid() during CPU initialization - one each for PMCEID0 and PMCEID1. In addition to building the register values, get_pmceid() clears an internal array mapping event numbers to their implementations (supported_event_map) before rebuilding it. This is an optimization since much of the logic is shared. However, since it was called twice, the contents of supported_event_map reflect only the events in PMCEID1 (the second call to get_pmceid()). Fix this bug by moving the initialization of PMCEID0 and PMCEID1 back into a single function call, and name it more appropriately since it is doing more than simply generating the contents of the PMCEID[01] registers. Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190123195814.29253-1-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-29target/arm: v8m: Ensure IDAU is respected if SAU is disabledThomas Roth1-9/+10
The current behavior of v8m_security_lookup in helper.c only checks whether the IDAU specifies a higher security if the SAU is enabled. If SAU.ALLNS is set to 1, this will lead to addresses being treated as non-secure, even though the IDAU indicates that they must be secure. This patch changes the behavior to also check the IDAU if the SAU is currently disabled. (This brings the behaviour here into line with the v8M Arm ARM SecurityCheck() pseudocode.) Signed-off-by: Thomas Roth <code@stacksmashing.net> Message-id: CAGGekkuc+-tvp5RJP7CM+Jy_hJF7eiRHZ96132sb=hPPCappKg@mail.gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: added pseudocode ref to the commit message, fixed comment style] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-29target/arm: Fix validation of 32-bit address spaces for aa32Richard Henderson1-7/+14
When tsz == 0, aarch32 selects the address space via exclusion, and there are no "top_bits" remaining that require validation. Fixes: ba97be9f4a4 Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190125184913.5970-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-28i386: Enable NPT and NRIPSAVE for AMD CPUsVitaly Kuznetsov1-0/+8
Modern AMD CPUs support NPT and NRIPSAVE features and KVM exposes these when present. NRIPSAVE apeared somewhere in Opteron_G3 lifetime (e.g. QuadCore AMD Opteron 2378 has is but QuadCore AMD Opteron HE 2344 doesn't), NPT was introduced a bit earlier. Add the FEAT_SVM leaf to Opteron_G4/G5 and EPYC/EPYC-IBPB cpu models. Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com> Message-Id: <20190121155051.5628-1-vkuznets@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-01-28i386: Update stepping of Cascadelake-ServerTao Xu1-1/+1
Update the stepping from 5 to 6, in order that the Cascadelake-Server CPU model can support AVX512VNNI and MSR based features exposed by ARCH_CAPABILITIES. Signed-off-by: Tao Xu <tao3.xu@intel.com> Message-Id: <20181227024304.12182-2-tao3.xu@intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2019-01-25Merge remote-tracking branch ↵Peter Maydell3-30/+73
'remotes/amarkovic/tags/mips-queue-january-25-2019' into staging MIPS queue for January 25, 2019 # gpg: Signature made Fri 25 Jan 2019 13:25:57 GMT # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-january-25-2019: docs/qemu-cpu-models: Add MIPS/nanoMIPS QEMU supported CPU models qemu-doc: Add nanoMIPS ISA information tests: tcg: mips: Remove old directories tests: tcg: mips: Add two new Makefiles tests: tcg: mips: Move source files to new locations MAINTAINERS: Update MIPS sections target/mips: Add I6500 core configuration target/mips: nanoMIPS: Fix branch handling disas: nanoMIPS: Amend DSP instructions related comments target/mips: Extend gen_scwp() functionality to support EVA target/mips: Correct the second argument type of cpu_supports_isa() target/mips: nanoMIPS: Rename macros for extracting 3-bit-coded GPR numbers target/mips: nanoMIPS: Remove an unused macro target/mips: nanoMIPS: Remove duplicate macro definitions Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-24target/mips: Add I6500 core configurationYongbok Kim1-0/+40
Add I6500 core configuration. Note that this configuration is supported only on best-effort basis due to the lack of certain features in QEMU. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-24target/mips: nanoMIPS: Fix branch handlingStefan Markovic1-0/+12
Fix nanoMIPS branch handling. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-24target/mips: Extend gen_scwp() functionality to support EVAAleksandar Markovic1-4/+6
Extend gen_scwp() functionality to support EVA by adding an additional argument, modify internals of the function to handle new functionality, and accordingly change its invocations. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-24target/mips: Correct the second argument type of cpu_supports_isa()Aleksandar Markovic2-2/+2
"insn_flags" bitfield was expanded from 32-bit to 64-bit in commit f9c9cd63e3. However, this was not reflected on the second argument of the function cpu_supports_isa(). By chance, this did not create some wrong behavior, since the left-most halves of all instances of the second argument are currently all zeros. However, this is still a bug waiting to happen. Correct this by changing the type of the second argument to be always 64-bit. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-24target/mips: nanoMIPS: Rename macros for extracting 3-bit-coded GPR numbersAleksandar Markovic1-13/+13
Rename macros for extracting 3-bit-coded GPR numbers, to achieve better consistency with the nanoMIPS documentation. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-24target/mips: nanoMIPS: Remove an unused macroAleksandar Markovic1-1/+0
Remove a macro that is never used. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-24target/mips: nanoMIPS: Remove duplicate macro definitionsAleksandar Markovic1-10/+0
Several macros were defined twice, with identical values, so remove duplicates. Previously added in 80845edf37b. This reverts commit 6bfa9f4c9cf24d6cfaaa227722e9cdcca1ad6fe9. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-24ppc: e6500 registers SPR 604 twiceJon Diekema1-8/+0
When using the e6500 CPU, QEMU generates a fatal error after complaining about registering SPR 604 twice. Building and testing with commit 9b2e891ec5ccdb4a7d583b77988848282606fdea shows the issue: qemu-system-ppc64 --version QEMU emulator version 3.1.50 (v3.1.0-456-g9b2e891ec5-dirty) Copyright (c) 2003-2018 Fabrice Bellard and the QEMU Project developers qemu-system-ppc64 -M none -cpu e6500 Error: Trying to register SPR 604 (25c) twice ! Signed-off-by: Jon Diekema <jon.diekema@ge.com> Message-Id: <CALvuzg43uSodseEHjNaRcPFBKKPTY2mcppUbYgiLL=QO9RxX_Q@mail.gmail.com> [removed duplicated mail header in the commit message] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-01-23Merge remote-tracking branch 'remotes/xtensa/tags/20190122-xtensa' into stagingPeter Maydell12-1531/+1685
target/xtensa: zero overhead loops rework/helpers split - change xtensa zero overhead loops implementation to avoid invalidation of TBs corresponding to previous loop body when a new loop is encountered; - extract helper function groups from op_helper.c and move them into separate source files: exc_helper.c (exception helpers), win_helper.c (windowed registers helpers), fpu_helper.c (floating point helpers), mmu_helper.c (memory management helpers) and dbg_helper.c (native debug helpers). # gpg: Signature made Tue 22 Jan 2019 18:44:17 GMT # gpg: using RSA key 51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <filippov@cadence.com>" # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20190122-xtensa: target/xtensa: move non-HELPER functions to helper.c target/xtensa: drop dump_state helper target/xtensa: extract interrupt and exception helpers target/xtensa: extract debug helpers target/xtensa: extract MMU helpers target/xtensa: extract windowed registers helpers target/xtensa: extract FPU helpers target/xtensa: rework zero overhead loops implementation Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-23Merge remote-tracking branch ↵Peter Maydell3-15/+30
'remotes/edgar/tags/edgar/xilinx-next-2019-01-22.for-upstream' into staging Pullreq 2019-01-22 # gpg: Signature made Tue 22 Jan 2019 11:42:41 GMT # gpg: using RSA key 29C596780F6BCA83 # gpg: Good signature from "Edgar E. Iglesias (Xilinx key) <edgar.iglesias@xilinx.com>" # gpg: aka "Edgar E. Iglesias <edgar.iglesias@gmail.com>" # Primary key fingerprint: AC44 FEDC 14F7 F1EB EDBF 4151 29C5 9678 0F6B CA83 * remotes/edgar/tags/edgar/xilinx-next-2019-01-22.for-upstream: target/microblaze: Add props enabling exceptions on failed bus accesses hw/microblaze: s3adsp1800: Create an unimplemented GPIO area target/microblaze: Switch to transaction_failed hook Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-22target/microblaze: Add props enabling exceptions on failed bus accessesEdgar E. Iglesias2-1/+13
Add MicroBlaze CPU properties to enable exceptions on failed bus accesses. Reviewed-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2019-01-22target/microblaze: Switch to transaction_failed hookPeter Maydell3-14/+17
Switch the microblaze target from the old unassigned_access hook to the transaction_failed hook. The notable difference is that rather than it being called for all physical memory accesses which fail (including those made by DMA devices or by the gdbstub), it is only called for those made by the CPU via its MMU. For microblaze this makes no difference because none of the target CPU code needs to make loads or stores by physical address. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> [EI: Add space in qemu_log()] Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2019-01-22ppc: Fix duplicated typedefs to be able to compile with Clang in gnu99 modeThomas Huth1-4/+5
When compiling the ppc code with clang and -std=gnu99, there are a couple of warnings/errors like this one: CC ppc64-softmmu/hw/intc/xics.o In file included from hw/intc/xics.c:35: include/hw/ppc/xics.h:43:25: error: redefinition of typedef 'ICPState' is a C11 feature [-Werror,-Wtypedef-redefinition] typedef struct ICPState ICPState; ^ target/ppc/cpu.h:1181:25: note: previous definition is here typedef struct ICPState ICPState; ^ Work around the problems by including the proper headers in spapr.h and by using struct forward declarations in cpu.h. Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-01-21Merge remote-tracking branch ↵Peter Maydell6-641/+960
'remotes/amarkovic/tags/mips-queue-january-17-2019-v2' into staging MIPS queue for January 17, 2019 - v2 # gpg: Signature made Fri 18 Jan 2019 15:55:35 GMT # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-january-17-2019-v2: target/mips: Introduce 32 R5900 multimedia registers target/mips: Rename 'rn' to 'register_name' target/mips: Add CP0 register MemoryMapID target/mips: Amend preprocessor constants for CP0 registers target/mips: Update ITU to handle bus errors target/mips: Update ITU to utilize SAARI and SAAR CP0 registers target/mips: Add field and R/W access to ITU control register ICR0 target/mips: Provide R/W access to SAARI and SAAR CP0 registers target/mips: Add fields for SAARI and SAAR CP0 registers target/mips: Use preprocessor constants for 32 major CP0 registers target/mips: Add preprocessor constants for 32 major CP0 registers target/mips: Move comment containing summary of CP0 registers Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21target/arm: Implement PMSWINCAaron Lindsay1-2/+37
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181211151945.29137-14-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21target/arm: PMU: Set PMCR.N to 4Aaron Lindsay1-5/+5
This both advertises that we support four counters and enables them because the pmu_num_counters() reads this value from PMCR. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-13-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21target/arm: PMU: Add instruction and cycle eventsAaron Lindsay1-46/+44
The instruction event is only enabled when icount is used, cycles are always supported. Always defining get_cycle_count (but altering its behavior depending on CONFIG_USER_ONLY) allows us to remove some CONFIG_USER_ONLY #defines throughout the rest of the code. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-12-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPERAaron Lindsay2-17/+282
Add arrays to hold the registers, the definitions themselves, access functions, and logic to reset counters when PMCR.P is set. Update filtering code to support counters other than PMCCNTR. Support migration with raw read/write functions. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181211151945.29137-11-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0Aaron Lindsay4-11/+79
This commit doesn't add any supported events, but provides the framework for adding them. We store the pm_event structs in a simple array, and provide the mapping from the event numbers to array indexes in the supported_event_map array. Because the value of PMCEID[01] depends upon which events are supported at runtime, generate it dynamically. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-10-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]Aaron Lindsay2-4/+19
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-9-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21target/arm: Define FIELDs for ID_DFR0Aaron Lindsay1-0/+9
This is immediately necessary for the PMUv3 implementation to check ID_DFR0.PerfMon to enable/disable specific features, but defines the full complement of fields for possible future use elsewhere. Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-8-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21target/arm: Implement PMOVSSETAaron Lindsay1-0/+28
Add an array for PMOVSSET so we only define it for v7ve+ platforms Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181211151945.29137-7-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21target/arm: Allow AArch32 access for PMCCFILTRAaron Lindsay1-1/+26
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181211151945.29137-6-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21target/arm: Filter cycle counter based on PMCCFILTR_EL0Aaron Lindsay3-8/+101
Rename arm_ccnt_enabled to pmu_counter_enabled, and add logic to only return 'true' if the specified counter is enabled and neither prohibited or filtered. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Signed-off-by: Aaron Lindsay <aclindsa@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181211151945.29137-5-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21target/arm: Swap PMU values before/after migrationsAaron Lindsay2-2/+28
Because of the PMU's design, many register accesses have side effects which are inter-related, meaning that the normal method of saving CP registers can result in inconsistent state. These side-effects are largely handled in pmu_op_start/finish functions which can be called before and after the state is saved/restored. By doing this and adding raw read/write functions for the affected registers, we avoid migration-related inconsistencies. Signed-off-by: Aaron Lindsay <aclindsa@gmail.com> Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-4-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21target/arm: Reorganize PMCCNTR accessesAaron Lindsay2-53/+98
pmccntr_read and pmccntr_write contained duplicate code that was already being handled by pmccntr_sync. Consolidate the duplicated code into two functions: pmccntr_op_start and pmccntr_op_finish. Add a companion to c15_ccnt in CPUARMState so that we can simultaneously save both the architectural register value and the last underlying cycle count - this ensures time isn't lost and will also allow us to access the 'old' architectural register value in order to detect overflows in later patches. Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Signed-off-by: Aaron Lindsay <aclindsa@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20181211151945.29137-3-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21target/arm: Tidy TBI handling in gen_a64_set_pcRichard Henderson1-43/+23
We can perform this with fewer operations. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-32-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21target/arm: Enable PAuth for user-onlyRichard Henderson2-0/+63
Add 4 attributes that controls the EL1 enable bits, as we may not always want to turn on pointer authentication with -cpu max. However, by default they are enabled. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190108223129.5570-31-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21target/arm: Enable PAuth for -cpu maxRichard Henderson1-0/+4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-30-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21target/arm: Add PAuth system registersRichard Henderson1-0/+70
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-29-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21target/arm: Implement pauth_computepacRichard Henderson1-1/+241
This is the main crypto routine, an implementation of QARMA. This matches, as much as possible, ARM pseudocode. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190108223129.5570-28-richard.henderson@linaro.org [PMM: fixed minor checkpatch nits] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21target/arm: Implement pauth_addpacRichard Henderson1-1/+41
This is not really functional yet, because the crypto is not yet implemented. This, however follows the AddPAC pseudo function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-27-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21target/arm: Implement pauth_authRichard Henderson1-1/+20
This is not really functional yet, because the crypto is not yet implemented. This, however follows the Auth pseudo function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-26-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21target/arm: Implement pauth_stripRichard Henderson1-1/+13
Stripping out the authentication data does not require any crypto, it merely requires the virtual address parameters. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21target/arm: Reuse aa64_va_parameters for setting tbflagsRichard Henderson2-81/+24
The arm_regime_tbi{0,1} functions are replacable with the new function by giving the lowest and highest address. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190108223129.5570-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21target/arm: Decode TBID from TCRRichard Henderson2-3/+12
Use TBID in aa64_va_parameters depending on the data parameter. This automatically updates all existing users of the function. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190108223129.5570-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-21target/arm: Add aa64_va_parameters_bothRichard Henderson2-5/+20
We will want to check TBI for I and D simultaneously. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190108223129.5570-22-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.1 at 2024-08-25 01:42:05 +0000