index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target
Age
Commit message (
Expand
)
Author
Files
Lines
2020-12-19
qapi: Use QAPI_LIST_PREPEND() where possible
Eric Blake
6
-46
/
+9
2020-12-17
target/riscv: cpu: Set XLEN independently from target
Alistair Francis
1
-9
/
+16
2020-12-17
target/riscv: csr: Remove compile time XLEN checks
Alistair Francis
2
-88
/
+92
2020-12-17
target/riscv: cpu_helper: Remove compile time XLEN checks
Alistair Francis
1
-5
/
+7
2020-12-17
target/riscv: cpu: Remove compile time XLEN checks
Alistair Francis
1
-9
/
+10
2020-12-17
target/riscv: Specify the XLEN for CPUs
Alistair Francis
1
-10
/
+23
2020-12-17
target/riscv: Add a riscv_cpu_is_32bit() helper function
Alistair Francis
2
-0
/
+11
2020-12-17
target/riscv: fpu_helper: Match function defs in HELPER macros
Alistair Francis
2
-24
/
+8
2020-12-17
target/riscv: Add a TYPE_RISCV_CPU_BASE CPU
Alistair Francis
1
-0
/
+6
2020-12-17
target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
Alex Richardson
1
-2
/
+2
2020-12-17
target/riscv: Fix the bug of HLVX/HLV/HSV
Yifei Jiang
1
-1
/
+2
2020-12-16
i386: tcg: remove inline from cpu_load_eflags
Claudio Fontana
2
-13
/
+15
2020-12-16
i386: move TCG cpu class initialization to tcg/
Claudio Fontana
19
-148
/
+238
2020-12-16
x86/cpu: Add AVX512_FP16 cpu feature
Cathy Zhang
2
-1
/
+3
2020-12-16
i386: move hyperv_limits initialization to x86_cpu_realizefn()
Vitaly Kuznetsov
3
-1
/
+18
2020-12-16
i386: move hyperv_version_id initialization to x86_cpu_realizefn()
Vitaly Kuznetsov
3
-2
/
+17
2020-12-16
i386: move hyperv_interface_id initialization to x86_cpu_realizefn()
Vitaly Kuznetsov
3
-6
/
+19
2020-12-16
i386: move hyperv_vendor_id initialization to x86_cpu_realizefn()
Vitaly Kuznetsov
3
-17
/
+34
2020-12-16
i386: move cpu dump out of helper.c into cpu-dump.c
Claudio Fontana
4
-514
/
+539
2020-12-16
i386: move TCG accel files into tcg/
Claudio Fontana
16
-13
/
+14
2020-12-16
i386: move hax accel files into hax/
Claudio Fontana
12
-10
/
+11
2020-12-16
i386: move whpx accel files into whpx/
Claudio Fontana
7
-5
/
+6
2020-12-16
i386: move kvm accel files into kvm/
Claudio Fontana
16
-14
/
+17
2020-12-15
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20201215'...
Peter Maydell
5
-4
/
+70
2020-12-15
Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request...
Peter Maydell
3
-34
/
+28
2020-12-15
sparc: Check dev->realized at sparc_set_nwindows()
Eduardo Habkost
1
-0
/
+6
2020-12-15
arm/cpu64: Register "aarch64" as class property
Eduardo Habkost
1
-10
/
+6
2020-12-15
i386: Register feature bit properties as class properties
Eduardo Habkost
1
-24
/
+16
2020-12-15
target/nios2: Use deposit32() to update ipending register
Peter Maydell
1
-2
/
+1
2020-12-15
target/nios2: Move nios2_check_interrupts() into target/nios2
Peter Maydell
2
-2
/
+9
2020-12-15
target/nios2: Move IIC code into CPU object proper
Peter Maydell
2
-1
/
+30
2020-12-15
target/openrisc: Move pic_cpu code into CPU object proper
Peter Maydell
2
-1
/
+32
2020-12-14
Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.0-pul...
Peter Maydell
1
-3
/
+3
2020-12-14
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-20201213' into ...
Peter Maydell
12
-354
/
+408
2020-12-14
target/ppc: Introduce an mmu_is_64bit() helper
Greg Kurz
7
-12
/
+17
2020-12-14
ppc/translate: Use POWERPC_MMU_64 to detect 64-bit MMU models
Stephane Duverger
1
-2
/
+2
2020-12-14
target/ppc: Remove "compat" property of server class POWER CPUs
Greg Kurz
1
-59
/
+0
2020-12-14
ppc/translate: Rewrite gen_lxvdsx to use gvec primitives
Giuseppe Musacchio
1
-23
/
+23
2020-12-14
ppc/translate: Raise exceptions after setting the cc
Giuseppe Musacchio
1
-14
/
+14
2020-12-14
ppc/translate: Delay NaN checking after comparison
Giuseppe Musacchio
1
-38
/
+42
2020-12-14
ppc/translate: Turn the helper macros into functions
Giuseppe Musacchio
1
-105
/
+123
2020-12-14
ppc/translate: Fix unordered f64/f128 comparisons
Giuseppe Musacchio
1
-10
/
+22
2020-12-14
target/ppc: replaced the TODO with LOG_UNIMP and add break for silence warnings
Chen Qun
1
-2
/
+3
2020-12-13
target/mips: Use FloatRoundMode enum for FCR31 modes conversion
Philippe Mathieu-Daudé
2
-2
/
+3
2020-12-13
target/mips: Remove unused headers from fpu_helper.c
Philippe Mathieu-Daudé
1
-4
/
+0
2020-12-13
target/mips: Inline cpu_mips_realize_env() in mips_cpu_realizefn()
Philippe Mathieu-Daudé
1
-12
/
+8
2020-12-13
target/mips: Move cpu definitions, reset() and realize() to cpu.c
Philippe Mathieu-Daudé
3
-244
/
+243
2020-12-13
target/mips: Move mips_cpu_add_definition() from helper.c to cpu.c
Philippe Mathieu-Daudé
2
-33
/
+33
2020-12-13
target/mips: Extract cpu_supports*/cpu_set* translate.c
Philippe Mathieu-Daudé
2
-18
/
+18
2020-12-13
target/mips: Do not initialize MT registers if MT ASE absent
Philippe Mathieu-Daudé
1
-0
/
+4
[next]