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2020-03-03Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf3' i...Peter Maydell10-133/+1223
2020-02-28target/arm: Implement ARMv8.3-CCIDXPeter Maydell2-1/+35
2020-02-28target/arm: Implement v8.4-RCPCPeter Maydell3-1/+96
2020-02-28target/arm: Implement v8.3-RCPCPeter Maydell3-0/+30
2020-02-28target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0Peter Maydell1-2/+2
2020-02-28target/arm: Split VMINMAXNM decodeRichard Henderson2-77/+44
2020-02-28target/arm: Split VFM decodeRichard Henderson2-14/+55
2020-02-28target/arm: Add formats for some vfp 2 and 3-register insnsRichard Henderson1-90/+60
2020-02-28target/arm: Remove ARM_FEATURE_VFP*Richard Henderson5-37/+0
2020-02-28target/arm: Move the vfp decodetree calls next to the base isaRichard Henderson1-54/+29
2020-02-28target/arm: Move VLLDM and VLSTM to vfp.decodeRichard Henderson3-44/+50
2020-02-28target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insnRichard Henderson1-4/+0
2020-02-28target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmacRichard Henderson4-6/+36
2020-02-28target/arm: Add missing checks for fpsp_v2Richard Henderson1-9/+69
2020-02-28target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3Richard Henderson1-16/+8
2020-02-28target/arm: Perform fpdp_v2 check firstRichard Henderson1-69/+71
2020-02-28target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfpRichard Henderson3-5/+20
2020-02-28target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}Richard Henderson1-0/+18
2020-02-28target/arm: Rename isar_feature_aa32_fpdp_v2Richard Henderson2-22/+22
2020-02-28target/arm: Add isar_feature_aa32_vfp_simdRichard Henderson5-14/+25
2020-02-28target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfnRichard Henderson1-0/+1
2020-02-27target/riscv: Emulate TIME CSRs for privileged modeAnup Patel3-4/+92
2020-02-27target/riscv: Allow enabling the Hypervisor extensionAlistair Francis2-0/+6
2020-02-27target/riscv: Add the MSTATUS_MPV_ISSET helper macroAlistair Francis4-4/+15
2020-02-27target/riscv: Add support for the 32-bit MSTATUSH CSRAlistair Francis6-0/+62
2020-02-27target/riscv: Set htval and mtval2 on execptionsAlistair Francis1-0/+10
2020-02-27target/riscv: Raise the new execptions when 2nd stage translation failsAlistair Francis1-6/+18
2020-02-27target/riscv: Implement second stage MMUAlistair Francis2-19/+175
2020-02-27target/riscv: Allow specifying MMU stageAlistair Francis1-9/+28
2020-02-27target/riscv: Respect MPRV and SPRV for floating point opsAlistair Francis1-1/+15
2020-02-27target/riscv: Mark both sstatus and msstatus_hs as dirtyAlistair Francis1-0/+13
2020-02-27target/riscv: Disable guest FP support based on virtual statusAlistair Francis1-0/+3
2020-02-27target/riscv: Only set TB flags with FP status if enabledAlistair Francis1-1/+4
2020-02-27target/riscv: Remove the hret instructionAlistair Francis2-6/+0
2020-02-27target/riscv: Add hfence instructionsAlistair Francis2-9/+54
2020-02-27target/riscv: Add Hypervisor trap return supportAlistair Francis1-10/+52
2020-02-27target/riscv: Add hypvervisor trap supportAlistair Francis1-10/+59
2020-02-27target/riscv: Generate illegal instruction on WFI when V=1Alistair Francis1-2/+3
2020-02-27target/ricsv: Flush the TLB on virtulisation mode changesAlistair Francis1-0/+5
2020-02-27target/riscv: Add support for virtual interrupt settingAlistair Francis1-5/+28
2020-02-27target/riscv: Extend the SIP CSR to support virtulisationAlistair Francis1-1/+12
2020-02-27target/riscv: Extend the MIE CSR to support virtulisationAlistair Francis1-4/+20
2020-02-27target/riscv: Set VS bits in mideleg for Hyp extensionAlistair Francis1-0/+3
2020-02-27target/riscv: Add virtual register swapping functionAlistair Francis3-0/+79
2020-02-27target/riscv: Add Hypervisor machine CSRs accessesAlistair Francis1-0/+27
2020-02-27target/riscv: Add Hypervisor virtual CSRs accessesAlistair Francis1-0/+116
2020-02-27target/riscv: Add Hypervisor CSR access functionsAlistair Francis1-2/+134
2020-02-27target/riscv: Dump Hypervisor registers if enabledAlistair Francis1-0/+33
2020-02-27target/riscv: Print priv and virt in disas logAlistair Francis1-0/+8
2020-02-27target/riscv: Fix CSR perm checking for HS modeAlistair Francis1-4/+14
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