| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-07-01 | target/arm: Enable FEAT_Debugv8p8 for -cpu max | Gustavo Romero | 2 | -4/+4 |
| 2024-07-01 | target/arm: Move initialization of debug ID registers | Gustavo Romero | 2 | -3/+30 |
| 2024-07-01 | target/arm: Fix indentation | Gustavo Romero | 1 | -1/+1 |
| 2024-07-01 | target/arm: Delete dead code from disas_simd_indexed | Richard Henderson | 1 | -93/+0 |
| 2024-07-01 | target/arm: Convert FCMLA to decodetree | Richard Henderson | 2 | -170/+74 |
| 2024-07-01 | target/arm: Convert FCADD to decodetree | Richard Henderson | 2 | -23/+13 |
| 2024-07-01 | target/arm: Add data argument to do_fp3_vector | Richard Henderson | 1 | -26/+26 |
| 2024-07-01 | target/arm: Convert BFMMLA, SMMLA, UMMLA, USMMLA to decodetree | Richard Henderson | 2 | -28/+12 |
| 2024-07-01 | target/arm: Convert BFMLALB, BFMLALT to decodetree | Richard Henderson | 2 | -48/+31 |
| 2024-07-01 | target/arm: Convert BFDOT to decodetree | Richard Henderson | 2 | -15/+7 |
| 2024-07-01 | target/arm: Convert SUDOT, USDOT to decodetree | Richard Henderson | 2 | -27/+11 |
| 2024-07-01 | target/arm: Convert SDOT, UDOT to decodetree | Richard Henderson | 2 | -26/+35 |
| 2024-07-01 | target/arm: Convert SQRDMLAH, SQRDMLSH to decodetree | Richard Henderson | 4 | -124/+180 |
| 2024-07-01 | target/arm: Fix FJCVTZS vs flush-to-zero | Richard Henderson | 1 | -9/+9 |
| 2024-07-01 | target/arm: Fix SQDMULH (by element) with Q=0 | Richard Henderson | 1 | -8/+16 |
| 2024-07-01 | target/arm: Fix VCMLA Dd, Dn, Dm[idx] | Richard Henderson | 1 | -2/+2 |
| 2024-06-30 | target/i386: Advertise MWAIT iff host supports | Zide Chen | 2 | -14/+9 |
| 2024-06-28 | target/i386/sev: Fix printf formats | Richard Henderson | 1 | -6/+11 |
| 2024-06-28 | target/i386/sev: Use size_t for object sizes | Richard Henderson | 2 | -9/+9 |
| 2024-06-28 | target/i386: SEV: store pointer to decoded id_auth in SevSnpGuest | Paolo Bonzini | 1 | -5/+8 |
| 2024-06-28 | target/i386: SEV: rename sev_snp_guest->id_auth | Paolo Bonzini | 1 | -6/+6 |
| 2024-06-28 | target/i386: SEV: store pointer to decoded id_block in SevSnpGuest | Paolo Bonzini | 1 | -5/+6 |
| 2024-06-28 | target/i386: SEV: rename sev_snp_guest->id_block | Paolo Bonzini | 1 | -6/+6 |
| 2024-06-28 | target/i386: remove unused enum | Paolo Bonzini | 1 | -16/+0 |
| 2024-06-28 | target/i386: give CC_OP_POPCNT low bits corresponding to MO_TL | Paolo Bonzini | 2 | -4/+12 |
| 2024-06-28 | target/i386: use cpu_cc_dst for CC_OP_POPCNT | Paolo Bonzini | 4 | -6/+6 |
| 2024-06-28 | target/i386: fix CC_OP dump | Paolo Bonzini | 1 | -63/+64 |
| 2024-06-27 | target/riscv: Apply modularized matching conditions for icount trigger | Alvin Chang | 1 | -1/+1 |
| 2024-06-27 | target/riscv: Apply modularized matching conditions for watchpoint | Alvin Chang | 1 | -20/+6 |
| 2024-06-27 | target/riscv: Add functions for common matching conditions of trigger | Alvin Chang | 1 | -23/+78 |
| 2024-06-26 | target/riscv: Remove extension auto-update check statements | Frank Chang | 1 | -119/+0 |
| 2024-06-26 | target/riscv: Add Zc extension implied rule | Frank Chang | 1 | -0/+34 |
| 2024-06-26 | target/riscv: Add multi extension implied rules | Frank Chang | 1 | -0/+340 |
| 2024-06-26 | target/riscv: Add MISA extension implied rules | Frank Chang | 1 | -1/+49 |
| 2024-06-26 | target/riscv: Introduce extension implied rule helpers | Frank Chang | 1 | -0/+121 |
| 2024-06-26 | target/riscv: Introduce extension implied rules definition | Frank Chang | 2 | -0/+31 |
| 2024-06-26 | target/riscv: fix instructions count handling in icount mode | Clément Léger | 1 | -13/+17 |
| 2024-06-26 | target/riscv: Fix froundnx.h nanbox check | Branislav Brzak | 1 | -1/+1 |
| 2024-06-26 | target/riscv: Support the version for ss1p13 | Fea.Wang | 2 | -1/+9 |
| 2024-06-26 | target/riscv: Reserve exception codes for sw-check and hw-err | Fea.Wang | 1 | -0/+2 |
| 2024-06-26 | target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 | Fea.Wang | 2 | -0/+33 |
| 2024-06-26 | target/riscv: Add 'P1P13' bit in SMSTATEEN0 | Fea.Wang | 2 | -0/+9 |
| 2024-06-26 | target/riscv: Define macros and variables for ss1p13 | Fea.Wang | 2 | -1/+4 |
| 2024-06-26 | target/riscv: Reuse the conversion function of priv_spec | Jim Shu | 3 | -10/+6 |
| 2024-06-26 | target/riscv/kvm: handle the exit with debug reason | Chao Du | 1 | -0/+20 |
| 2024-06-26 | target/riscv/kvm: add software breakpoints support | Chao Du | 1 | -0/+69 |
| 2024-06-26 | target/riscv: zvbb implies zvkb | Jerry Zhang Jian | 1 | -0/+4 |
| 2024-06-26 | target/riscv: Move Guest irqs out of the core local irqs range. | Rajnesh Kanwal | 2 | -2/+10 |
| 2024-06-26 | target/riscv: Extend virtual irq csrs masks to be 64 bit wide. | Rajnesh Kanwal | 1 | -7/+7 |
| 2024-06-24 | Merge tag 'pull-maintainer-june24-240624-1' of https://gitlab.com/stsquad/qem... | Richard Henderson | 6 | -6/+6 |
