riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-01-10	target/riscv: implement svade	Daniel Henrique Barboza	3	-0/+7
2024-01-10	target/riscv: add 'rva22u64' CPU	Daniel Henrique Barboza	3	-0/+27
2024-01-10	riscv-qmp-cmds.c: add profile flags in cpu-model-expansion	Daniel Henrique Barboza	1	-0/+14
2024-01-10	target/riscv/tcg: validate profiles during finalize	Daniel Henrique Barboza	1	-0/+69
2024-01-10	target/riscv/tcg: honor user choice for G MISA bits	Daniel Henrique Barboza	1	-25/+48
2024-01-10	target/riscv/tcg: add hash table insert helpers	Daniel Henrique Barboza	1	-12/+16
2024-01-10	target/riscv/tcg: handle profile MISA bits	Daniel Henrique Barboza	1	-0/+21
2024-01-10	target/riscv/tcg: add riscv_cpu_write_misa_bit()	Daniel Henrique Barboza	1	-14/+18
2024-01-10	target/riscv/tcg: add MISA user options hash	Daniel Henrique Barboza	1	-1/+14
2024-01-10	target/riscv/tcg: add user flag for profile support	Daniel Henrique Barboza	1	-0/+80
2024-01-10	target/riscv/kvm: add 'rva22u64' flag as unavailable	Daniel Henrique Barboza	1	-1/+6
2024-01-10	target/riscv: add rva22u64 profile definition	Daniel Henrique Barboza	2	-0/+44
2024-01-10	riscv-qmp-cmds.c: expose named features in cpu_model_expansion	Daniel Henrique Barboza	1	-5/+25
2024-01-10	target/riscv/tcg: add 'zic64b' support	Daniel Henrique Barboza	4	-0/+34
2024-01-10	target/riscv: add zicbop extension flag	Daniel Henrique Barboza	2	-0/+5
2024-01-10	target/riscv: add rv64i CPU	Daniel Henrique Barboza	2	-0/+48
2024-01-10	target/riscv/tcg: update priv_ver on user_set extensions	Daniel Henrique Barboza	1	-0/+32
2024-01-10	target/riscv/tcg: do not use "!generic" CPU checks	Daniel Henrique Barboza	1	-4/+9
2024-01-10	target/riscv: create TYPE_RISCV_VENDOR_CPU	Daniel Henrique Barboza	2	-9/+22
2024-01-10	target/riscv: Add support for Zacas extension	Weiwei Li	6	-0/+165
2024-01-10	target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong()	Daniel Henrique Barboza	1	-19/+21
2024-01-10	target/riscv/kvm: add RISCV_CONFIG_REG()	Daniel Henrique Barboza	1	-14/+11
2024-01-10	target/riscv/kvm: change timer regs size to u64	Daniel Henrique Barboza	1	-13/+13
2024-01-10	target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64	Daniel Henrique Barboza	1	-3/+8
2024-01-10	target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32	Daniel Henrique Barboza	1	-3/+8
2024-01-10	target/riscv/cpu.c: fix machine IDs getters	Daniel Henrique Barboza	1	-6/+6
2024-01-10	target/riscv/pmp: Use hwaddr instead of target_ulong for RV32	Ivan Klokov	2	-18/+16
2024-01-10	target/riscv: Not allow write mstatus_vs without RVV	LIU Zhiwei	1	-1/+4
2024-01-10	target/riscv: Fix th.dcache.cval1 priviledge check	LIU Zhiwei	1	-1/+1
2024-01-10	target/riscv: The whole vector register move instructions depend on vsew	Max Chou	1	-2/+1
2024-01-10	target/riscv: Add vill check for whole vector register move instructions	Max Chou	1	-2/+3
2024-01-08	Replace "iothread lock" with "BQL" in comments	Stefan Hajnoczi	2	-3/+3
2024-01-08	qemu/main-loop: rename qemu_cond_wait_iothread() to qemu_cond_wait_bql()	Stefan Hajnoczi	2	-2/+2
2024-01-08	qemu/main-loop: rename QEMU_IOTHREAD_LOCK_GUARD to BQL_LOCK_GUARD	Stefan Hajnoczi	4	-5/+5
2024-01-08	system/cpus: rename qemu_mutex_lock_iothread() to bql_lock()	Stefan Hajnoczi	35	-211/+211
2024-01-08	Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging	Peter Maydell	1	-7/+7
2024-01-06	target/loongarch: move translate modules to tcg/	Song Gao	24	-14/+20
2024-01-06	target/loongarch/meson: move gdbstub.c to loongarch.ss	Song Gao	1	-1/+1
2024-01-05	target/riscv: Fix mcycle/minstret increment behavior	Xu Lu	1	-7/+7
2024-01-05	target/sparc: Simplify qemu_irq_ack	Clément Chigot	2	-2/+2
2024-01-05	target: Use generic cpu_model_from_type()	Gavin Shan	8	-16/+8
2024-01-05	target/xtensa: Use generic cpu_list()	Gavin Shan	2	-12/+0
2024-01-05	target/tricore: Use generic cpu_list()	Gavin Shan	2	-26/+0
2024-01-05	target/sh4: Use generic cpu_list()	Gavin Shan	2	-20/+0
2024-01-05	target/rx: Use generic cpu_list()	Gavin Shan	2	-19/+0
2024-01-05	target/riscv: Use generic cpu_list()	Gavin Shan	2	-31/+0
2024-01-05	target/openrisc: Use generic cpu_list()	Gavin Shan	2	-45/+0
2024-01-05	target/mips: Use generic cpu_list()	Gavin Shan	2	-13/+0
2024-01-05	target/m68k: Use generic cpu_list()	Gavin Shan	2	-44/+0
2024-01-05	target/loongarch: Use generic cpu_list()	Gavin Shan	2	-19/+0