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2022-02-16target/riscv: Implement AIA mtopi, stopi, and vstopi CSRsAnup Patel1-0/+156
2022-02-16target/riscv: Implement AIA interrupt filtering CSRsAnup Patel1-0/+23
2022-02-16target/riscv: Implement AIA hvictl and hviprioX CSRsAnup Patel3-1/+131
2022-02-16target/riscv: Implement AIA CSRs for 64 local interrupts on RV32Anup Patel4-120/+474
2022-02-16target/riscv: Implement AIA local interrupt prioritiesAnup Patel4-21/+294
2022-02-16target/riscv: Allow AIA device emulation to set ireg rmw callbackAnup Patel2-0/+37
2022-02-16target/riscv: Add defines for AIA CSRsAnup Patel1-0/+119
2022-02-16target/riscv: Add AIA cpu featureAnup Patel1-1/+2
2022-02-16target/riscv: Allow setting CPU feature from machine/device emulationAnup Patel2-8/+8
2022-02-16target/riscv: Improve delivery of guest external interruptsAnup Patel1-0/+13
2022-02-16target/riscv: Implement hgeie and hgeip CSRsAnup Patel6-38/+121
2022-02-16target/riscv: Implement SGEIP bit in hip and hie CSRsAnup Patel3-8/+16
2022-02-16target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-modeAnup Patel1-1/+1
2022-02-16target/riscv: Fix vill field write in vtypeLIU Zhiwei1-0/+1
2022-02-16target/riscv: Add XVentanaCondOps custom extensionPhilipp Tomsich6-0/+83
2022-02-16target/riscv: iterate over a table of decodersPhilipp Tomsich1-5/+27
2022-02-16target/riscv: access cfg structure through DisasContextPhilipp Tomsich1-4/+4
2022-02-16target/riscv: access configuration through cfg_ptr in DisasContextPhilipp Tomsich4-69/+97
2022-02-16target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptrPhilipp Tomsich1-0/+2
2022-02-16target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUC...Philipp Tomsich1-37/+41
2022-02-16target/riscv: correct "code should not be reached" for x-rv128Frédéric Pétrot2-2/+4
2022-02-13Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220210' into s...Peter Maydell22-2150/+521
2022-02-09target/i386: use CPU_LOG_INT for IRQ servicingAlex Bennée1-2/+2
2022-02-09target/ppc: Change VSX instructions behavior to fill with zerosVíctor Colombo2-14/+16
2022-02-09target/ppc: books: Remove excp_model argument from ppc_excp_apply_ailFabiano Rosas1-12/+13
2022-02-09target/ppc: Assert if MSR bits differ from msr_mask during exceptionsFabiano Rosas1-58/+6
2022-02-09target/ppc: powerpc_excp: Move common code to the caller functionFabiano Rosas1-48/+9
2022-02-09target/ppc: Remove powerpc_excp_legacyFabiano Rosas1-474/+3
2022-02-09target/ppc: 7xx: Set SRRs directly in exception codeFabiano Rosas1-11/+2
2022-02-09target/ppc: 7xx: Software TLB cleanupFabiano Rosas1-20/+6
2022-02-09target/ppc: 7xx: System Reset cleanupFabiano Rosas1-16/+2
2022-02-09target/ppc: 7xx: System Call exception cleanupFabiano Rosas1-8/+13
2022-02-09target/ppc: 7xx: Program exception cleanupFabiano Rosas1-4/+0
2022-02-09target/ppc: 7xx: External interrupt cleanupFabiano Rosas1-37/+0
2022-02-09target/ppc: 7xx: Machine Check exception cleanupFabiano Rosas1-24/+0
2022-02-09target/ppc: Simplify powerpc_excp_7xxFabiano Rosas1-176/+9
2022-02-09target/ppc: Introduce powerpc_excp_7xxFabiano Rosas1-0/+469
2022-02-09target/ppc: Merge 7x5 and 7x0 exception model IDsFabiano Rosas3-13/+11
2022-02-09target/ppc: 6xx: Set SRRs directly in exception codeFabiano Rosas1-11/+2
2022-02-09target/ppc: 6xx: Software TLB exceptions cleanupFabiano Rosas1-20/+11
2022-02-09target/ppc: 6xx: System Reset interrupt cleanupFabiano Rosas1-16/+2
2022-02-09target/ppc: 6xx: System Call exception cleanupFabiano Rosas1-19/+2
2022-02-09target/ppc: 6xx: Program exception cleanupFabiano Rosas1-4/+0
2022-02-09target/ppc: 6xx: External interrupt cleanupFabiano Rosas1-37/+0
2022-02-09target/ppc: 6xx: Machine Check exception cleanupFabiano Rosas1-24/+0
2022-02-09target/ppc: 6xx: Critical exception cleanupFabiano Rosas1-15/+0
2022-02-09target/ppc: Simplify powerpc_excp_6xxFabiano Rosas1-154/+9
2022-02-09target/ppc: Introduce powerpc_excp_6xxFabiano Rosas1-0/+469
2022-02-09target/ppc: Merge exception model IDs for 6xx CPUsFabiano Rosas3-18/+13
2022-02-09target/ppc: Remove PowerPC 601 CPUsCédric Le Goater19-1615/+11