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| author | Anup Patel <anup.patel@wdc.com> | 2022-02-04 23:16:37 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-02-16 12:24:18 +1000 |
| commit | dceecac8a2fa36f6ab6927da2052f06e2de7a2a4 (patch) | |
| tree | 56db57dfcd7d2c96b60915ba6f923bab65191b6f /target | |
| parent | ac6bcf4d467a091b11ece782f4bf0a41e0f59cef (diff) | |
| download | qemu-dceecac8a2fa36f6ab6927da2052f06e2de7a2a4.zip qemu-dceecac8a2fa36f6ab6927da2052f06e2de7a2a4.tar.gz qemu-dceecac8a2fa36f6ab6927da2052f06e2de7a2a4.tar.bz2 | |
target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode
We should be returning illegal instruction trap when RV64 HS-mode tries
to access RV32 HS-mode CSR.
Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions")
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-2-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/csr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e5f9d4e..41a533a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -186,7 +186,7 @@ static RISCVException hmode(CPURISCVState *env, int csrno) static RISCVException hmode32(CPURISCVState *env, int csrno) { if (riscv_cpu_mxl(env) != MXL_RV32) { - if (riscv_cpu_virt_enabled(env)) { + if (!riscv_cpu_virt_enabled(env)) { return RISCV_EXCP_ILLEGAL_INST; } else { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; |