Age | Commit message (Expand) | Author | Files | Lines |
2023-03-05 | target/sparc: Use tlb_set_page_full | Richard Henderson | 1 | -67/+54 |
2023-03-04 | Merge tag 'pull-ppc-20230303' of https://gitlab.com/danielhb/qemu into staging | Peter Maydell | 1 | -0/+9 |
2023-03-03 | target/ppc/translate: Add dummy implementation for dcblc instruction | Bernhard Beschow | 1 | -0/+9 |
2023-03-03 | Merge tag 'pull-loongarch-20230303' of https://gitlab.com/gaosong/qemu into s... | Peter Maydell | 2 | -0/+3 |
2023-03-03 | Merge tag 'pull-riscv-to-apply-20230303' of https://gitlab.com/palmer-dabbelt... | Peter Maydell | 17 | -542/+504 |
2023-03-03 | target/loongarch: Implement Chip Configuraiton Version Register(0x0000) | Song Gao | 2 | -0/+3 |
2023-03-02 | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging | Peter Maydell | 10 | -3/+2312 |
2023-03-02 | Merge tag 'pull-monitor-2023-03-02' of https://repo.or.cz/qemu/armbru into st... | Peter Maydell | 11 | -141/+159 |
2023-03-02 | target/ppc: Restrict 'qapi-commands-machine.h' to system emulation | Philippe Mathieu-Daudé | 4 | -49/+53 |
2023-03-02 | target/loongarch: Restrict 'qapi-commands-machine.h' to system emulation | Philippe Mathieu-Daudé | 3 | -27/+38 |
2023-03-02 | target/i386: Restrict 'qapi-commands-machine.h' to system emulation | Philippe Mathieu-Daudé | 1 | -35/+39 |
2023-03-02 | target/arm: Restrict 'qapi-commands-machine.h' to system emulation | Philippe Mathieu-Daudé | 3 | -30/+29 |
2023-03-01 | Merge patch series "target/riscv: some vector_helper.c cleanups" | Palmer Dabbelt | 1 | -65/+39 |
2023-03-01 | target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig | Daniel Henrique Barboza | 1 | -10/+10 |
2023-03-01 | target/riscv/vector_helper.c: create vext_set_tail_elems_1s() | Daniel Henrique Barboza | 1 | -56/+30 |
2023-03-01 | Merge patch series "RISCVCPUConfig related cleanups" | Palmer Dabbelt | 1 | -61/+48 |
2023-03-01 | target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig | Daniel Henrique Barboza | 1 | -23/+9 |
2023-03-01 | target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers | Daniel Henrique Barboza | 1 | -38/+12 |
2023-03-01 | target/riscv/csr.c: simplify mctr() | Daniel Henrique Barboza | 1 | -3/+2 |
2023-03-01 | target/riscv/csr.c: use env_archcpu() in ctr() | Daniel Henrique Barboza | 1 | -2/+1 |
2023-03-01 | Merge patch series "target/riscv: Add support for Svadu extension" | Palmer Dabbelt | 5 | -8/+47 |
2023-03-01 | target/riscv: Export Svadu property | Weiwei Li | 1 | -0/+3 |
2023-03-01 | target/riscv: Add *envcfg.HADE related check in address translation | Weiwei Li | 2 | -2/+10 |
2023-03-01 | target/riscv: Add *envcfg.PBMTE related check in address translation | Weiwei Li | 2 | -2/+11 |
2023-03-01 | target/riscv: Add csr support for svadu | Weiwei Li | 3 | -6/+16 |
2023-03-01 | target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and h... | Weiwei Li | 1 | -4/+9 |
2023-03-01 | target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc... | Weiwei Li | 1 | -2/+6 |
2023-03-01 | target/riscv: Add support for Zicond extension | Weiwei Li | 5 | -0/+57 |
2023-03-01 | RISC-V: XTheadMemPair: Remove register restrictions for store-pair | Christoph Müllner | 1 | -4/+0 |
2023-03-01 | target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages | Shaobo Song | 1 | -1/+1 |
2023-03-01 | Merge patch series "target/riscv: Various fixes to gdbstub and CSR access" | Palmer Dabbelt | 2 | -240/+201 |
2023-03-01 | target/riscv: Group all predicate() routines together | Bin Meng | 1 | -90/+87 |
2023-03-01 | target/riscv: Drop priv level check in mseccfg predicate() | Bin Meng | 1 | -1/+1 |
2023-03-01 | target/riscv: Allow debugger to access sstc CSRs | Bin Meng | 1 | -5/+14 |
2023-03-01 | target/riscv: Allow debugger to access {h, s}stateen CSRs | Bin Meng | 1 | -2/+20 |
2023-03-01 | target/riscv: Allow debugger to access seed CSR | Bin Meng | 1 | -0/+4 |
2023-03-01 | target/riscv: Allow debugger to access user timer and counter CSRs | Bin Meng | 1 | -0/+4 |
2023-03-01 | target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml | Bin Meng | 1 | -75/+0 |
2023-03-01 | target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate() | Bin Meng | 1 | -0/+9 |
2023-03-01 | target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64 | Bin Meng | 1 | -15/+9 |
2023-03-01 | target/riscv: Simplify getting RISCVCPU pointer from env | Bin Meng | 1 | -24/+12 |
2023-03-01 | target/riscv: Simplify {read, write}_pmpcfg() a little bit | Bin Meng | 1 | -2/+2 |
2023-03-01 | target/riscv: Use 'bool' type for read_only | Bin Meng | 1 | -1/+1 |
2023-03-01 | target/riscv: Coding style fixes in csr.c | Bin Meng | 1 | -30/+32 |
2023-03-01 | target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled | Bin Meng | 1 | -3/+6 |
2023-03-01 | target/riscv: gdbstub: Minor change for better readability | Bin Meng | 1 | -2/+2 |
2023-03-01 | target/riscv: Use g_assert() for the predicate() NULL check | Bin Meng | 1 | -5/+1 |
2023-03-01 | target/riscv: Add some comments to clarify the priority policy of riscv_csrrw... | Bin Meng | 1 | -1/+10 |
2023-03-01 | target/riscv: gdbstub: Check priv spec version before reporting CSR | Bin Meng | 1 | -0/+3 |
2023-03-01 | Merge patch series "target/riscv: Some updates to float point related extensi... | Palmer Dabbelt | 6 | -170/+146 |