riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-08-26	arch_init.h: Don't include arch_init.h unnecessarily	Peter Maydell	2	-2/+0
2021-08-26	target/arm/cpu64: Validate sve vector lengths are supported	Andrew Jones	1	-56/+45
2021-08-26	target/arm/cpu64: Replace kvm_supported with sve_vq_supported	Andrew Jones	1	-8/+11
2021-08-26	target/arm/kvm64: Ensure sve vls map is completely clear	Andrew Jones	1	-1/+1
2021-08-26	target/arm/cpu: Introduce sve_vq_supported bitmap	Andrew Jones	2	-0/+6
2021-08-26	Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request'...	Peter Maydell	1	-1/+9
2021-08-25	Merge remote-tracking branch 'remotes/philmd/tags/mips-20210825' into staging	Peter Maydell	19	-486/+502
2021-08-25	i386/cpu: Remove AVX_VNNI feature from Cooperlake cpu model	Yang Zhong	1	-1/+1
2021-08-25	target/i386: Remove split lock detect in Snowridge CPU model	Chenyi Qiang	1	-0/+8
2021-08-25	target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian()	Philippe Mathieu-Daudé	3	-45/+50
2021-08-25	target/mips: Store CP0_Config0 in DisasContext	Philippe Mathieu-Daudé	2	-0/+2
2021-08-25	target/mips: Replace GET_LMASK64() macro by get_lmask(64) function	Philippe Mathieu-Daudé	1	-19/+16
2021-08-25	target/mips: Replace GET_LMASK() macro by get_lmask(32) function	Philippe Mathieu-Daudé	1	-11/+21
2021-08-25	target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st helpers	Philippe Mathieu-Daudé	1	-22/+33
2021-08-25	target/mips: Define gen_helper() macros in translate.h	Philippe Mathieu-Daudé	2	-12/+12
2021-08-25	target/mips: Use tcg_constant_i32() in generate_exception_err()	Philippe Mathieu-Daudé	1	-5/+2
2021-08-25	target/mips: Inline gen_helper_0e0i()	Philippe Mathieu-Daudé	1	-6/+2
2021-08-25	target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macros	Philippe Mathieu-Daudé	1	-5/+1
2021-08-25	target/mips: Simplify gen_helper() macros by using tcg_constant_i32()	Philippe Mathieu-Daudé	1	-15/+5
2021-08-25	target/mips: Use tcg_constant_i32() in gen_helper_0e2i()	Philippe Mathieu-Daudé	1	-12/+2
2021-08-25	target/mips: Remove gen_helper_1e2i()	Philippe Mathieu-Daudé	1	-6/+0
2021-08-25	target/mips: Remove gen_helper_0e3i()	Philippe Mathieu-Daudé	1	-6/+0
2021-08-25	target/mips: Remove duplicated check_cp1_enabled() calls in Loongson EXT	Philippe Mathieu-Daudé	1	-2/+0
2021-08-25	target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr	Philippe Mathieu-Daudé	1	-1/+1
2021-08-25	target/mips: Document Loongson-3A CPU definitions	Philippe Mathieu-Daudé	1	-2/+2
2021-08-25	target/mips: Convert Vr54xx MSA* opcodes to decodetree	Philippe Mathieu-Daudé	3	-53/+14
2021-08-25	target/mips: Convert Vr54xx MUL* opcodes to decodetree	Philippe Mathieu-Daudé	3	-24/+18
2021-08-25	target/mips: Convert Vr54xx MACC* opcodes to decodetree	Philippe Mathieu-Daudé	3	-16/+42
2021-08-25	target/mips: Introduce decodetree structure for NEC Vr54xx extension	Philippe Mathieu-Daudé	5	-0/+33
2021-08-25	target/mips: Extract NEC Vr54xx helpers to vr54xx_helper.c	Philippe Mathieu-Daudé	3	-118/+143
2021-08-25	target/mips: Extract NEC Vr54xx helper definitions	Philippe Mathieu-Daudé	2	-15/+27
2021-08-25	target/mips: Introduce generic TRANS() macro for decodetree helpers	Philippe Mathieu-Daudé	1	-0/+8
2021-08-25	target/mips: Rename 'rtype' as 'r'	Philippe Mathieu-Daudé	6	-46/+46
2021-08-25	target/mips: Merge 32-bit/64-bit Release6 decodetree definitions	Philippe Mathieu-Daudé	4	-40/+19
2021-08-25	target/mips: Decode vendor extensions before MIPS ISAs	Philippe Mathieu-Daudé	1	-3/+5
2021-08-25	target/mips: Simplify PREF opcode	Philippe Mathieu-Daudé	1	-6/+2
2021-08-25	target/mips: Remove JR opcode unused arguments	Philippe Mathieu-Daudé	1	-1/+1
2021-08-25	target/arm: kvm: use RCU_READ_LOCK_GUARD() in kvm_arch_fixup_msi_route()	Hamza Mahfooz	1	-9/+8
2021-08-25	target/arm: Implement M-profile trapping on division by zero	Peter Maydell	5	-6/+26
2021-08-25	target/arm: Re-indent sdiv and udiv helpers	Peter Maydell	1	-6/+9
2021-08-25	target/arm: Implement MVE interleaving loads/stores	Peter Maydell	4	-0/+495
2021-08-25	target/arm: Implement MVE scatter-gather immediate forms	Peter Maydell	4	-36/+150
2021-08-25	target/arm: Implement MVE scatter-gather insns	Peter Maydell	4	-0/+270
2021-08-25	target/arm: Implement MVE VCTP	Peter Maydell	6	-1/+58
2021-08-25	target/arm: Implement MVE VPNOT	Peter Maydell	4	-0/+38
2021-08-25	target/arm: Implement MVE VMOV to/from 2 general-purpose registers	Peter Maydell	4	-1/+91
2021-08-25	target/arm: Implement MVE VMAXA, VMINA	Peter Maydell	4	-0/+40
2021-08-25	target/arm: Implement MVE VQABS, VQNEG	Peter Maydell	4	-0/+50
2021-08-25	target/arm: Implement MVE saturating doubling multiply accumulates	Peter Maydell	4	-0/+120
2021-08-25	target/arm: Implement MVE VMLA	Peter Maydell	4	-0/+11