riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-01-14	target/mips: Introduce ase_msa_available() helper	Philippe Mathieu-Daudé	4	-11/+15
2021-01-14	target/mips/translate: Expose check_mips_64() to 32-bit mode	Philippe Mathieu-Daudé	2	-7/+3
2021-01-14	target/mips/translate: Extract decode_opc_legacy() from decode_opc()	Philippe Mathieu-Daudé	1	-20/+29
2021-01-14	target/mips: Only build TCG code when CONFIG_TCG is set	Philippe Mathieu-Daudé	1	-2/+6
2021-01-14	target/mips: Extract FPU specific definitions to translate.h	Philippe Mathieu-Daudé	2	-70/+71
2021-01-14	target/mips: Declare generic FPU / Coprocessor functions in translate.h	Philippe Mathieu-Daudé	2	-12/+24
2021-01-14	target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction	Philippe Mathieu-Daudé	2	-362/+368
2021-01-14	target/mips: Replace gen_exception_err(err=0) by gen_exception_end()	Philippe Mathieu-Daudé	1	-3/+3
2021-01-14	target/mips/translate: Add declarations for generic code	Philippe Mathieu-Daudé	2	-38/+57
2021-01-14	target/mips/translate: Extract DisasContext structure	Philippe Mathieu-Daudé	2	-37/+51
2021-01-14	target/mips: Rename translate_init.c as cpu-defs.c	Philippe Mathieu-Daudé	2	-1/+1
2021-01-14	target/mips: Move mmu_init() functions to tlb_helper.c	Philippe Mathieu-Daudé	3	-48/+47
2021-01-14	target/mips: Fix code style for checkpatch.pl	Philippe Mathieu-Daudé	1	-18/+18
2021-01-14	target/mips: Rename helper.c as tlb_helper.c	Philippe Mathieu-Daudé	2	-2/+2
2021-01-14	target/mips: Move common helpers from helper.c to cpu.c	Philippe Mathieu-Daudé	3	-207/+211
2021-01-14	target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs	Philippe Mathieu-Daudé	1	-2/+0
2021-01-14	target/mips: Add !CONFIG_USER_ONLY comment after #endif	Philippe Mathieu-Daudé	1	-5/+8
2021-01-14	target/mips: Extract FPU helpers to 'fpu_helper.h'	Philippe Mathieu-Daudé	10	-50/+68
2021-01-14	target/mips: Inline cpu_state_reset() in mips_cpu_reset()	Philippe Mathieu-Daudé	1	-17/+9
2021-01-14	target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6	Philippe Mathieu-Daudé	7	-236/+236
2021-01-14	target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5	Philippe Mathieu-Daudé	2	-3/+3
2021-01-14	target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3	Philippe Mathieu-Daudé	1	-2/+2
2021-01-14	target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2	Philippe Mathieu-Daudé	5	-75/+75
2021-01-14	target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1	Philippe Mathieu-Daudé	3	-30/+30
2021-01-14	target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6	Philippe Mathieu-Daudé	4	-7/+6
2021-01-14	target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5	Philippe Mathieu-Daudé	1	-2/+1
2021-01-14	target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3	Philippe Mathieu-Daudé	1	-2/+1
2021-01-14	target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2	Philippe Mathieu-Daudé	2	-4/+3
2021-01-14	target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1	Philippe Mathieu-Daudé	2	-7/+6
2021-01-14	target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()	Philippe Mathieu-Daudé	2	-1/+8
2021-01-14	target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1	Philippe Mathieu-Daudé	2	-11/+11
2021-01-14	target/mips/mips-defs: Reorder CPU_MIPS5 definition	Philippe Mathieu-Daudé	1	-2/+1
2021-01-14	target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment	Philippe Mathieu-Daudé	1	-6/+0
2021-01-14	target/mips/addr: Add translation helpers for KSEG1	Jiaxun Yang	2	-0/+12
2021-01-14	target/mips: Replace CP0_Config0 magic values by proper definitions	Philippe Mathieu-Daudé	1	-6/+8
2021-01-14	target/mips: Add CP0 Config0 register definitions for MIPS3 ISA	Philippe Mathieu-Daudé	1	-1/+9
2021-01-12	Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...	Peter Maydell	8	-21/+38
2021-01-12	target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns	Peter Maydell	1	-0/+7
2021-01-12	target/i386: Use X86Seg enum for segment registers	Philippe Mathieu-Daudé	4	-10/+10
2021-01-12	whpx: move whpx_lapic_state from header to c file	Yonggang Luo	2	-7/+7
2021-01-12	whpx: move internal definitions to whpx-internal.h	Paolo Bonzini	2	-0/+22
2021-01-12	whpx: rename whp-dispatch to whpx-internal.h	Paolo Bonzini	4	-11/+6
2021-01-12	target/arm: add aarch32 ID register fields to cpu.h	Leif Lindholm	1	-0/+28
2021-01-12	target/arm: add aarch64 ID register fields to cpu.h	Leif Lindholm	1	-0/+15
2021-01-12	target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h	Leif Lindholm	1	-0/+31
2021-01-12	target/arm: make ARMCPU.ctr 64-bit	Leif Lindholm	1	-1/+1
2021-01-12	target/arm: make ARMCPU.clidr 64-bit	Leif Lindholm	1	-1/+1
2021-01-12	target/arm: fix typo in cpu.h ID_AA64PFR1 field name	Leif Lindholm	1	-1/+1
2021-01-12	target/arm: enable Small Translation tables in max CPU	Rémi Denis-Courmont	1	-0/+1
2021-01-12	target/arm: ARMv8.4-TTST extension	Rémi Denis-Courmont	2	-2/+18