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Author
Files
Lines
2021-11-02
target/mips: Convert MSA ELM instruction format to decodetree
Philippe Mathieu-Daudé
2
-13
/
+52
2021-11-02
target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)
Philippe Mathieu-Daudé
2
-863
/
+106
2021-11-02
target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)
Philippe Mathieu-Daudé
2
-34
/
+9
2021-11-02
target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)
Philippe Mathieu-Daudé
2
-158
/
+35
2021-11-02
target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)
Philippe Mathieu-Daudé
2
-12
/
+11
2021-11-02
target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)
Philippe Mathieu-Daudé
2
-176
/
+76
2021-11-02
target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)
Philippe Mathieu-Daudé
2
-39
/
+38
2021-11-02
target/mips: Convert MSA VEC instruction format to decodetree
Philippe Mathieu-Daudé
2
-75
/
+31
2021-11-02
target/mips: Convert MSA 2R instruction format to decodetree
Philippe Mathieu-Daudé
2
-75
/
+19
2021-11-02
target/mips: Convert MSA FILL opcode to decodetree
Philippe Mathieu-Daudé
2
-12
/
+21
2021-11-02
target/mips: Convert MSA 2RF instruction format to decodetree
Philippe Mathieu-Daudé
2
-85
/
+53
2021-11-02
target/mips: Convert MSA load/store instruction format to decodetree
Philippe Mathieu-Daudé
2
-59
/
+36
2021-11-02
target/mips: Convert MSA I8 instruction format to decodetree
Philippe Mathieu-Daudé
2
-56
/
+27
2021-11-02
target/mips: Convert MSA SHF opcode to decodetree
Philippe Mathieu-Daudé
2
-17
/
+22
2021-11-02
target/mips: Convert MSA BIT instruction format to decodetree
Philippe Mathieu-Daudé
2
-97
/
+101
2021-11-02
target/mips: Convert MSA I5 instruction format to decodetree
Philippe Mathieu-Daudé
2
-77
/
+41
2021-11-02
target/mips: Convert MSA LDI opcode to decodetree
Philippe Mathieu-Daudé
2
-9
/
+21
2021-11-02
target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v
Philippe Mathieu-Daudé
2
-18
/
+17
2021-11-02
target/mips: Use enum definitions from CPUMIPSMSADataFormat enum
Philippe Mathieu-Daudé
1
-3
/
+3
2021-11-02
target/mips: Have check_msa_access() return a boolean
Philippe Mathieu-Daudé
1
-7
/
+18
2021-11-02
target/mips: Use dup_const() to simplify
Philippe Mathieu-Daudé
1
-20
/
+3
2021-11-02
target/mips: Adjust style in msa_translate_init()
Philippe Mathieu-Daudé
1
-1
/
+3
2021-11-02
target/mips: Fix MSA MSUBV.B opcode
Philippe Mathieu-Daudé
1
-16
/
+16
2021-11-02
target/mips: Fix MSA MADDV.B opcode
Philippe Mathieu-Daudé
1
-16
/
+16
2021-11-02
target/sparc: Set fault address in sparc_cpu_do_unaligned_access
Richard Henderson
2
-13
/
+20
2021-11-02
target/sparc: Split out build_sfsr
Richard Henderson
1
-26
/
+46
2021-11-02
target/sparc: Remove DEBUG_UNALIGNED
Richard Henderson
1
-9
/
+0
2021-11-02
target/sh4: Set fault address in superh_cpu_do_unaligned_access
Richard Henderson
1
-0
/
+5
2021-11-02
target/s390x: Implement s390x_cpu_record_sigbus
Richard Henderson
3
-10
/
+26
2021-11-02
target/ppc: Restrict ppc_cpu_do_unaligned_access to sysemu
Richard Henderson
2
-10
/
+6
2021-11-02
target/ppc: Set fault address in ppc_cpu_do_unaligned_access
Richard Henderson
1
-0
/
+14
2021-11-02
target/ppc: Move SPR_DSISR setting to powerpc_excp
Richard Henderson
1
-12
/
+9
2021-11-02
target/microblaze: Do not set MO_ALIGN for user-only
Richard Henderson
1
-0
/
+16
2021-11-02
target/arm: Implement arm_cpu_record_sigbus
Richard Henderson
4
-0
/
+10
2021-11-02
target/alpha: Implement alpha_cpu_record_sigbus
Richard Henderson
3
-11
/
+28
2021-11-02
target/xtensa: Make xtensa_cpu_tlb_fill sysemu only
Richard Henderson
3
-23
/
+3
2021-11-02
target/sparc: Make sparc_cpu_tlb_fill sysemu only
Richard Henderson
3
-27
/
+2
2021-11-02
target/sh4: Make sh4_cpu_tlb_fill sysemu only
Richard Henderson
3
-12
/
+5
2021-11-02
target/s390x: Implement s390_cpu_record_sigsegv
Richard Henderson
3
-12
/
+25
2021-11-02
target/s390x: Use probe_access_flags in s390_probe_access
Richard Henderson
1
-13
/
+5
2021-11-02
target/riscv: Make riscv_cpu_tlb_fill sysemu only
Richard Henderson
2
-21
/
+2
2021-11-02
target/ppc: Implement ppc_cpu_record_sigsegv
Richard Henderson
4
-9
/
+24
2021-11-02
target/openrisc: Make openrisc_cpu_tlb_fill sysemu only
Richard Henderson
4
-14
/
+6
2021-11-02
target/nios2: Implement nios2_cpu_record_sigsegv
Richard Henderson
3
-5
/
+14
2021-11-02
target/mips: Make mips_cpu_tlb_fill sysemu only
Richard Henderson
5
-69
/
+5
2021-11-02
target/microblaze: Make mb_cpu_tlb_fill sysemu only
Richard Henderson
3
-17
/
+6
2021-11-02
target/m68k: Make m68k_cpu_tlb_fill sysemu only
Richard Henderson
2
-6
/
+2
2021-11-02
target/i386: Implement x86_cpu_record_sigsegv
Richard Henderson
3
-7
/
+25
2021-11-02
target/hppa: Make hppa_cpu_tlb_fill sysemu only
Richard Henderson
4
-19
/
+6
2021-11-02
target/hexagon: Remove hexagon_cpu_tlb_fill
Richard Henderson
1
-23
/
+0
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