riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-05-06	target/loongarch: Implement vsrlr vsrar	Song Gao	5	-0/+176
2023-05-06	target/loongarch: Implement vsllwil vextl	Song Gao	5	-0/+89
2023-05-06	target/loongarch: Implement vsll vsrl vsra vrotr	Song Gao	3	-0/+108
2023-05-06	target/loongarch: Implement LSX logic instructions	Song Gao	5	-0/+94
2023-05-06	target/loongarch: Implement vmskltz/vmskgez/vmsknz	Song Gao	5	-0/+141
2023-05-06	target/loongarch: Implement vsigncov	Song Gao	5	-0/+75
2023-05-06	target/loongarch: Implement vexth	Song Gao	5	-0/+82
2023-05-06	target/loongarch: Implement vsat	Song Gao	5	-0/+168
2023-05-06	target/loongarch: Implement vdiv/vmod	Song Gao	5	-0/+105
2023-05-06	target/loongarch: Implement vmadd/vmsub/vmaddw{ev/od}	Song Gao	5	-0/+817
2023-05-06	target/loongarch: Implement vmul/vmuh/vmulw{ev/od}	Song Gao	5	-0/+732
2023-05-06	target/loongarch: Implement vmax/vmin	Song Gao	5	-0/+319
2023-05-06	target/loongarch: Implement vadda	Song Gao	5	-0/+87
2023-05-06	target/loongarch: Implement vabsd	Song Gao	5	-0/+133
2023-05-06	target/loongarch: Implement vavg/vavgr	Song Gao	5	-0/+281
2023-05-06	target/loongarch: Implement vaddw/vsubw	Song Gao	5	-0/+1116
2023-05-06	target/loongarch: Implement vhaddw/vhsubw	Song Gao	5	-0/+150
2023-05-06	target/loongarch: Implement vsadd/vssub	Song Gao	3	-0/+51
2023-05-06	target/loongarch: Implement vneg	Song Gao	3	-0/+37
2023-05-06	target/loongarch: Implement vaddi/vsubi	Song Gao	3	-0/+62
2023-05-06	target/loongarch: Implement vadd/vsub	Song Gao	5	-0/+139
2023-05-06	target/loongarch: Add CHECK_SXE maccro for check LSX enable	Song Gao	3	-0/+15
2023-05-06	target/loongarch: meson.build support build LSX	Song Gao	4	-0/+13
2023-05-06	target/loongarch: Add LSX data type VReg	Song Gao	5	-11/+117
2023-05-05	Merge tag 'pull-tcg-20230505' of https://gitlab.com/rth7680/qemu into staging	Richard Henderson	15	-260/+233
2023-05-05	target/sparc: Use cpu_ld*_code_mmu	Richard Henderson	1	-4/+6
2023-05-05	target/sparc: Use MO_ALIGN where required	Richard Henderson	1	-32/+34
2023-05-05	target/hppa: Use MO_ALIGN for system UNALIGN()	Richard Henderson	1	-1/+1
2023-05-05	target/alpha: Use MO_ALIGN where required	Richard Henderson	1	-16/+20
2023-05-05	target/alpha: Use MO_ALIGN for system UNALIGN()	Richard Henderson	1	-1/+1
2023-05-05	target/xtensa: Finish conversion to tcg_gen_qemu_{ld, st}_*	Richard Henderson	1	-2/+2
2023-05-05	target/sparc: Finish conversion to tcg_gen_qemu_{ld, st}_*	Richard Henderson	1	-15/+28
2023-05-05	target/s390x: Finish conversion to tcg_gen_qemu_{ld, st}_*	Richard Henderson	1	-81/+71
2023-05-05	target/mips: Finish conversion to tcg_gen_qemu_{ld,st}_*	Richard Henderson	2	-5/+5
2023-05-05	target/m68k: Finish conversion to tcg_gen_qemu_{ld,st}_*	Richard Henderson	1	-51/+25
2023-05-05	target/Hexagon: Finish conversion to tcg_gen_qemu_{ld, st}_*	Richard Henderson	4	-42/+40
2023-05-05	target/cris: Finish conversion to tcg_gen_qemu_{ld,st}_*	Richard Henderson	1	-14/+4
2023-05-05	target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_*	Richard Henderson	1	-8/+8
2023-05-05	tcg: ppc64: Fix mask generation for vextractdm	Shivaprasad G Bhat	1	-1/+1
2023-05-05	ppc: spapr: cleanup cr get/set with helpers.	Harsh Prateek Bora	5	-34/+26
2023-05-05	target/riscv: add Ventana's Veyron V1 CPU	Rahul Pathak	3	-0/+43
2023-05-05	riscv: Make sure an exception is raised if a pte is malformed	Alexandre Ghiti	2	-4/+12
2023-05-05	target/riscv: Fix Guest Physical Address Translation	Irina Ryapolova	1	-9/+16
2023-05-05	target/riscv: Restore the predicate() NULL check behavior	Bin Meng	1	-2/+9
2023-05-05	target/riscv: add TYPE_RISCV_DYNAMIC_CPU	Daniel Henrique Barboza	3	-5/+21
2023-05-05	target/riscv: add query-cpy-definitions support	Daniel Henrique Barboza	2	-1/+55
2023-05-05	target/riscv: add CPU QOM header	Daniel Henrique Barboza	2	-45/+71
2023-05-05	target/riscv: Reorg sum check in get_physical_address	Richard Henderson	1	-11/+11
2023-05-05	target/riscv: Reorg access check in get_physical_address	Richard Henderson	1	-33/+36
2023-05-05	target/riscv: Merge checks for reserved pte flags	Richard Henderson	1	-6/+6