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Lines
2021-11-03
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
Richard Henderson
4
-0
/
+46
2021-11-03
Merge remote-tracking branch 'remotes/vivier/tags/trivial-branch-for-6.2-pull...
Richard Henderson
5
-7
/
+7
2021-11-03
Merge remote-tracking branch 'remotes/rth/tags/pull-arm-20211102-2' into staging
Richard Henderson
5
-28
/
+51
2021-11-03
Merge remote-tracking branch 'remotes/berrange/tags/hmp-x-qmp-620-pull-reques...
Richard Henderson
1
-6
/
+0
2021-11-02
Merge remote-tracking branch 'remotes/philmd/tags/mips-20211102' into staging
Richard Henderson
4
-2087
/
+845
2021-11-02
hvf: arm: Ignore cache operations on MMIO
Alexander Graf
1
-0
/
+7
2021-11-02
target/arm: Use tcg_constant_i32() in gen_rev16()
Philippe Mathieu-Daudé
1
-2
/
+1
2021-11-02
target/arm: Use tcg_constant_i64() in do_sat_addsub_64()
Philippe Mathieu-Daudé
1
-9
/
+8
2021-11-02
target/arm: Use the constant variant of store_cpu_field() when possible
Philippe Mathieu-Daudé
1
-15
/
+6
2021-11-02
target/arm: Introduce store_cpu_field_constant() helper
Philippe Mathieu-Daudé
1
-0
/
+3
2021-11-02
target/arm: Use tcg_constant_i32() in op_smlad()
Philippe Mathieu-Daudé
1
-2
/
+1
2021-11-02
target/arm: Advertise MVE to gdb when present
Peter Maydell
1
-0
/
+25
2021-11-02
monitor: remove 'info ioapic' HMP command
Daniel P. Berrangé
1
-6
/
+0
2021-11-02
KVM: SVM: add migration support for nested TSC scaling
Maxim Levitsky
4
-0
/
+46
2021-11-02
target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU
Philippe Mathieu-Daudé
1
-1
/
+0
2021-11-02
target/mips: Fix Loongson-3A4000 MSAIR config register
Philippe Mathieu-Daudé
1
-0
/
+1
2021-11-02
target/mips: Remove one MSA unnecessary decodetree overlap group
Philippe Mathieu-Daudé
1
-182
/
+180
2021-11-02
target/mips: Remove generic MSA opcode
Philippe Mathieu-Daudé
2
-9
/
+0
2021-11-02
target/mips: Convert CTCMSA opcode to decodetree
Philippe Mathieu-Daudé
2
-58
/
+16
2021-11-02
target/mips: Convert CFCMSA opcode to decodetree
Philippe Mathieu-Daudé
2
-9
/
+23
2021-11-02
target/mips: Convert MSA MOVE.V opcode to decodetree
Philippe Mathieu-Daudé
2
-6
/
+20
2021-11-02
target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree
Philippe Mathieu-Daudé
2
-88
/
+19
2021-11-02
target/mips: Convert MSA COPY_U opcode to decodetree
Philippe Mathieu-Daudé
2
-26
/
+41
2021-11-02
target/mips: Convert MSA ELM instruction format to decodetree
Philippe Mathieu-Daudé
2
-13
/
+52
2021-11-02
target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)
Philippe Mathieu-Daudé
2
-863
/
+106
2021-11-02
target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)
Philippe Mathieu-Daudé
2
-34
/
+9
2021-11-02
target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)
Philippe Mathieu-Daudé
2
-158
/
+35
2021-11-02
target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)
Philippe Mathieu-Daudé
2
-12
/
+11
2021-11-02
target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)
Philippe Mathieu-Daudé
2
-176
/
+76
2021-11-02
target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)
Philippe Mathieu-Daudé
2
-39
/
+38
2021-11-02
target/mips: Convert MSA VEC instruction format to decodetree
Philippe Mathieu-Daudé
2
-75
/
+31
2021-11-02
target/mips: Convert MSA 2R instruction format to decodetree
Philippe Mathieu-Daudé
2
-75
/
+19
2021-11-02
target/mips: Convert MSA FILL opcode to decodetree
Philippe Mathieu-Daudé
2
-12
/
+21
2021-11-02
target/mips: Convert MSA 2RF instruction format to decodetree
Philippe Mathieu-Daudé
2
-85
/
+53
2021-11-02
target/mips: Convert MSA load/store instruction format to decodetree
Philippe Mathieu-Daudé
2
-59
/
+36
2021-11-02
target/mips: Convert MSA I8 instruction format to decodetree
Philippe Mathieu-Daudé
2
-56
/
+27
2021-11-02
target/mips: Convert MSA SHF opcode to decodetree
Philippe Mathieu-Daudé
2
-17
/
+22
2021-11-02
target/mips: Convert MSA BIT instruction format to decodetree
Philippe Mathieu-Daudé
2
-97
/
+101
2021-11-02
target/mips: Convert MSA I5 instruction format to decodetree
Philippe Mathieu-Daudé
2
-77
/
+41
2021-11-02
target/mips: Convert MSA LDI opcode to decodetree
Philippe Mathieu-Daudé
2
-9
/
+21
2021-11-02
target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v
Philippe Mathieu-Daudé
2
-18
/
+17
2021-11-02
target/mips: Use enum definitions from CPUMIPSMSADataFormat enum
Philippe Mathieu-Daudé
1
-3
/
+3
2021-11-02
target/mips: Have check_msa_access() return a boolean
Philippe Mathieu-Daudé
1
-7
/
+18
2021-11-02
target/mips: Use dup_const() to simplify
Philippe Mathieu-Daudé
1
-20
/
+3
2021-11-02
target/mips: Adjust style in msa_translate_init()
Philippe Mathieu-Daudé
1
-1
/
+3
2021-11-02
target/mips: Fix MSA MSUBV.B opcode
Philippe Mathieu-Daudé
1
-16
/
+16
2021-11-02
target/mips: Fix MSA MADDV.B opcode
Philippe Mathieu-Daudé
1
-16
/
+16
2021-11-02
target/sparc: Set fault address in sparc_cpu_do_unaligned_access
Richard Henderson
2
-13
/
+20
2021-11-02
target/sparc: Split out build_sfsr
Richard Henderson
1
-26
/
+46
2021-11-02
target/sparc: Remove DEBUG_UNALIGNED
Richard Henderson
1
-9
/
+0
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