riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-11-18	Merge remote-tracking branch 'remotes/vivier2/tags/ppc-for-4.2-pull-request' ...	Peter Maydell	1	-8/+13
2019-11-18	spapr/kvm: Set default cpu model for all machine classes	David Gibson	1	-8/+13
2019-11-14	target/riscv: Remove atomic accesses to MIP CSR	Alistair Francis	4	-43/+21
2019-11-14	remove unnecessary ifdef TARGET_RISCV64	hiroyuki.obinata	1	-3/+1
2019-11-12	target/microblaze: Plug temp leak around eval_cond_jmp()	Edgar E. Iglesias	1	-1/+4
2019-11-12	target/microblaze: Plug temp leaks with delay slot setup	Edgar E. Iglesias	1	-12/+14
2019-11-12	target/microblaze: Plug temp leaks for loads/stores	Edgar E. Iglesias	1	-26/+20
2019-11-06	target/sparc: Define an enumeration for accessing env->regwptr	Richard Henderson	1	-0/+33
2019-11-01	target/arm: Allow reading flags from FPSCR for M-profile	Christophe Lyon	1	-2/+3
2019-11-01	target/arm/kvm: host cpu: Add support for sve<N> properties	Andrew Jones	4	-17/+35
2019-11-01	target/arm/cpu64: max cpu: Support sve properties with KVM	Andrew Jones	3	-42/+242
2019-11-01	target/arm/kvm: scratch vcpu: Preserve input kvm_vcpu_init features	Andrew Jones	3	-7/+25
2019-11-01	target/arm/kvm64: max cpu: Enable SVE when available	Andrew Jones	4	-4/+65
2019-11-01	target/arm/kvm64: Add kvm_arch_get/put_sve	Andrew Jones	1	-28/+155
2019-11-01	target/arm/cpu64: max cpu: Introduce sve<N> properties	Andrew Jones	5	-2/+250
2019-11-01	target/arm: Allow SVE to be disabled via a CPU property	Andrew Jones	3	-9/+48
2019-11-01	target/arm/monitor: Introduce qmp_query_cpu_model_expansion	Andrew Jones	1	-0/+146
2019-10-30	Merge remote-tracking branch 'remotes/stsquad/tags/pull-tcg-plugins-281019-4'...	Peter Maydell	11	-32/+21
2019-10-29	Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20191028' into staging	Peter Maydell	1	-2/+1
2019-10-28	target/riscv: PMP violation due to wrong size parameter	Dayeol Lee	1	-1/+12
2019-10-28	target/openrisc: fetch code with translator_ld	Emilio G. Cota	1	-1/+1
2019-10-28	target/xtensa: fetch code with translator_ld	Emilio G. Cota	1	-2/+2
2019-10-28	target/sparc: fetch code with translator_ld	Emilio G. Cota	1	-1/+1
2019-10-28	target/riscv: fetch code with translator_ld	Emilio G. Cota	1	-1/+1
2019-10-28	target/alpha: fetch code with translator_ld	Emilio G. Cota	1	-1/+1
2019-10-28	target/m68k: fetch code with translator_ld	Emilio G. Cota	1	-1/+1
2019-10-28	target/hppa: fetch code with translator_ld	Emilio G. Cota	1	-1/+1
2019-10-28	target/i386: fetch code with translator_ld	Emilio G. Cota	1	-5/+5
2019-10-28	target/sh4: fetch code with translator_ld	Emilio G. Cota	1	-2/+2
2019-10-28	target/ppc: fetch code with translator_ld	Emilio G. Cota	1	-5/+3
2019-10-28	target/arm: fetch code with translator_ld	Emilio G. Cota	1	-12/+3
2019-10-28	cputlb: ensure _cmmu helper functions follow the naming standard	Alex Bennée	1	-2/+1
2019-10-28	target/riscv: Make the priv register writable by GDB	Jonathan Behrens	1	-0/+9
2019-10-28	target/riscv: Expose "priv" register for GDB for reads	Jonathan Behrens	1	-0/+23
2019-10-28	target/riscv: Tell gdbstub the correct number of CSRs	Jonathan Behrens	1	-2/+2
2019-10-28	linux-user/riscv: Propagate fault address	Giuseppe Musacchio	1	-1/+4
2019-10-28	RISC-V: Implement cpu_do_transaction_failed	Palmer Dabbelt	3	-7/+13
2019-10-28	RISC-V: Handle bus errors in the page table walker	Palmer Dabbelt	1	-3/+9
2019-10-28	riscv: Skip checking CSR privilege level in debugger mode	Bin Meng	1	-1/+4
2019-10-28	cputlb: ensure _cmmu helper functions follow the naming standard	Alex Bennée	1	-2/+1
2019-10-26	i386: implement IGNNE	Paolo Bonzini	2	-8/+30
2019-10-26	target/i386: introduce cpu_set_fpus	Paolo Bonzini	1	-4/+8
2019-10-26	target/i386: move FERR handling to target/i386	Paolo Bonzini	2	-2/+27
2019-10-26	core: replace getpagesize() with qemu_real_host_page_size	Wei Yang	1	-1/+1
2019-10-26	Merge commit 'df84f17' into HEAD	Paolo Bonzini	5	-6/+99
2019-10-25	target/mips: Refactor handling of vector compare 'less than' (signed) instruc...	Filip Bozuta	1	-30/+50
2019-10-25	target/mips: Refactor handling of vector compare 'equal' instructions	Filip Bozuta	1	-30/+50
2019-10-25	target/mips: Demacro LMI decoder	Aleksandar Markovic	1	-74/+174
2019-10-25	target/mips: msa: Split helpers for ASUB_<S\|U>.<B\|H\|W\|D>	Aleksandar Markovic	3	-26/+193
2019-10-25	target/mips: msa: Split helpers for HSUB_<S\|U>.<H\|W\|D>	Aleksandar Markovic	3	-21/+129