riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-01-23	Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...	Peter Maydell	1	-0/+1
2021-01-21	x86/cpu: Use max host physical address if -cpu max option is applied	Yang Weijiang	1	-0/+1
2021-01-21	s390x: Use strpadcpy for copying vm name	Miroslav Rezanina	2	-9/+10
2021-01-21	s390x/tcg: Ignore register content if b1/b2 is zero when handling EXECUTE	David Hildenbrand	1	-2/+2
2021-01-21	s390x/tcg: Don't ignore content in r0 when not specified via "b" or "x"	David Hildenbrand	2	-10/+13
2021-01-21	s390x/tcg: Fix RISBHG	David Hildenbrand	1	-10/+8
2021-01-21	s390x/tcg: Fix ALGSI	David Hildenbrand	1	-1/+1
2021-01-19	target/arm/m_helper: Silence GCC 10 maybe-uninitialized error	Philippe Mathieu-Daudé	1	-1/+1
2021-01-19	target/arm: Update REV, PUNPK for pred_desc	Richard Henderson	2	-13/+8
2021-01-19	target/arm: Update ZIP, UZP, TRN for pred_desc	Richard Henderson	2	-17/+13
2021-01-19	target/arm: Update PFIRST, PNEXT for pred_desc	Richard Henderson	2	-6/+7
2021-01-19	target/arm: Introduce PREDDESC field definitions	Richard Henderson	1	-0/+9
2021-01-19	target/arm: refactor vae1_tlbmask()	Rémi Denis-Courmont	1	-14/+11
2021-01-19	target/arm: enable Secure EL2 in max CPU	Rémi Denis-Courmont	1	-0/+1
2021-01-19	target/arm: Implement SCR_EL2.EEL2	Rémi Denis-Courmont	4	-8/+36
2021-01-19	target/arm: revector to run-time pick target EL	Rémi Denis-Courmont	1	-2/+21
2021-01-19	target/arm: set HPFAR_EL2.NS on secure stage 2 faults	Rémi Denis-Courmont	4	-0/+13
2021-01-19	target/arm: secure stage 2 translation regime	Rémi Denis-Courmont	3	-25/+81
2021-01-19	target/arm: generalize 2-stage page-walk condition	Rémi Denis-Courmont	1	-7/+6
2021-01-19	target/arm: translate NS bit in page-walks	Rémi Denis-Courmont	1	-0/+12
2021-01-19	target/arm: do S1_ptw_translate() before address space lookup	Rémi Denis-Courmont	1	-3/+6
2021-01-19	target/arm: handle VMID change in secure state	Rémi Denis-Courmont	1	-4/+9
2021-01-19	target/arm: add ARMv8.4-SEL2 system registers	Rémi Denis-Courmont	2	-0/+31
2021-01-19	target/arm: add MMU stage 1 for Secure EL2	Rémi Denis-Courmont	5	-58/+124
2021-01-19	target/arm: add 64-bit S-EL2 to EL exception table	Rémi Denis-Courmont	2	-7/+7
2021-01-19	target/arm: Define isar_feature function to test for presence of SEL2	Rémi Denis-Courmont	1	-0/+5
2021-01-19	target/arm: factor MDCR_EL2 common handling	Rémi Denis-Courmont	1	-16/+22
2021-01-19	target/arm: use arm_hcr_el2_eff() where applicable	Rémi Denis-Courmont	1	-13/+18
2021-01-19	target/arm: use arm_is_el2_enabled() where applicable	Rémi Denis-Courmont	3	-29/+16
2021-01-19	target/arm: add arm_is_el2_enabled() helper	Rémi Denis-Courmont	1	-0/+17
2021-01-19	target/arm: remove redundant tests	Rémi Denis-Courmont	2	-10/+8
2021-01-19	target/arm: Use object_property_add_bool for "sve" property	Richard Henderson	1	-14/+10
2021-01-19	target/arm: Add cpu properties to control pauth	Richard Henderson	4	-4/+60
2021-01-19	target/arm: Implement an IMPDEF pauth algorithm	Richard Henderson	2	-9/+33
2021-01-18	Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-misc-1801...	Peter Maydell	12	-1184/+99
2021-01-18	riscv: Add semihosting support	Keith Packard	4	-1/+58
2021-01-18	semihosting: Change common-semi API to be architecture-independent	Keith Packard	3	-11/+9
2021-01-18	semihosting: Move ARM semihosting code to shared directories	Keith Packard	2	-1123/+0
2021-01-18	target/arm: use official org.gnu.gdb.aarch64.sve layout for registers	Alex Bennée	2	-47/+30
2021-01-18	gdbstub: drop CPUEnv from gdb_exit()	Alex Bennée	3	-3/+3
2021-01-16	target/riscv: Generate the GDB XML file for CSR registers dynamically	Bin Meng	3	-264/+58
2021-01-16	target/riscv: Add CSR name in the CSR function table	Bin Meng	2	-84/+249
2021-01-16	target/riscv: Make csr_ops[CSR_TABLE_SIZE] external	Bin Meng	2	-9/+9
2021-01-16	target/riscv/pmp: Raise exception if no PMP entry is configured	Atish Patra	3	-2/+8
2021-01-16	gdb: riscv: Add target description	Sylvain Pelissier	1	-0/+13
2021-01-14	target/mips: Remove vendor specific CPU definitions	Philippe Mathieu-Daudé	2	-10/+7
2021-01-14	target/mips: Remove CPU_NANOMIPS32 definition	Philippe Mathieu-Daudé	2	-5/+2
2021-01-14	target/mips: Remove CPU_R5900 definition	Philippe Mathieu-Daudé	1	-1/+0
2021-01-14	target/mips: Convert Rel6 LL/SC opcodes to decodetree	Philippe Mathieu-Daudé	2	-2/+2
2021-01-14	target/mips: Convert Rel6 LLD/SCD opcodes to decodetree	Philippe Mathieu-Daudé	2	-2/+3