riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-08-21	target/xtensa: implement FPU division and square root	Max Filippov	1	-0/+4
2020-08-21	target/xtensa: add DFPU registers and opcodes	Max Filippov	1	-2/+32
2020-08-21	target/xtensa: don't access BR regfile directly	Max Filippov	1	-7/+7
2020-08-21	target/xtensa: rename FPU2000 translators and helpers	Max Filippov	1	-10/+10
2019-05-15	target/xtensa: implement exclusive access option	Max Filippov	1	-0/+1
2019-05-10	target/xtensa: implement MPU option	Max Filippov	1	-0/+5
2019-02-28	target/xtensa: only rotate window in the retw helper	Max Filippov	1	-1/+1
2019-02-28	target/xtensa: move WINDOW_BASE SR update to postprocessing	Max Filippov	1	-2/+1
2019-01-24	target/xtensa: fix access to the INTERRUPT SR	Max Filippov	1	-0/+2
2019-01-13	target/xtensa: drop dump_state helper	Max Filippov	1	-1/+0
2019-01-11	target/xtensa: rework zero overhead loops implementation	Max Filippov	1	-2/+0
2018-10-01	target/xtensa: extract test for window underflow exception	Max Filippov	1	-0/+1
2018-10-01	target/xtensa: extract test for an illegal instruction	Max Filippov	1	-0/+1
2018-03-16	target/xtensa: add linux-user support	Max Filippov	1	-0/+4
2017-01-25	Merge remote-tracking branch 'remotes/xtensa/tags/20170124-xtensa' into staging	Peter Maydell	1	-2/+7
2017-01-16	target-xtensa: implement RER/WER instructions	Max Filippov	1	-0/+3
2017-01-15	target/xtensa: implement MEMCTL SR	Max Filippov	1	-0/+1
2017-01-15	target/xtensa: refactor CCOUNT/CCOMPARE	Max Filippov	1	-2/+3
2017-01-10	target-xtensa: Use clz opcode	Richard Henderson	1	-2/+0
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-0/+58