riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-03-12	target/xtensa: Prefer fast cpu_env() over slower CPU QOM cast macro	Philippe Mathieu-Daudé	1	-6/+3
2024-01-19	target/xtensa: use generic instruction breakpoint infrastructure	Max Filippov	1	-0/+12
2024-01-05	target/xtensa: Use generic cpu_list()	Gavin Shan	1	-9/+0
2023-03-07	gdbstub: move register helpers into standalone include	Alex Bennée	1	-1/+1
2022-11-01	accel/tcg: Remove will_exit argument from cpu_restore_state	Richard Henderson	1	-3/+3
2022-02-21	exec/exec-all: Move 'qemu/log.h' include in units requiring it	Philippe Mathieu-Daudé	1	-0/+1
2021-11-02	target/xtensa: Make xtensa_cpu_tlb_fill sysemu only	Richard Henderson	1	-21/+1
2021-05-20	target/xtensa: clean up unaligned access	Max Filippov	1	-7/+6
2021-02-05	cpu: move cc->transaction_failed to tcg_ops	Claudio Fontana	1	-2/+2
2020-08-21	target/xtensa: add geometry to xtensa_get_regfile_by_name	Max Filippov	1	-1/+3
2020-04-07	target/xtensa: statically allocate xtensa_insnbufs in DisasContext	Max Filippov	1	-0/+1
2019-06-10	target/xtensa: Use env_cpu, env_archcpu	Richard Henderson	1	-1/+1
2019-05-21	Merge remote-tracking branch 'remotes/xtensa/tags/20190520-xtensa' into staging	Peter Maydell	1	-0/+1
2019-05-10	target/xtensa: get rid of centralized SR properties	Max Filippov	1	-0/+1
2019-05-10	tcg: Use CPUClass::tlb_fill in cputlb.c	Richard Henderson	1	-6/+0
2019-05-10	target/xtensa: Convert to CPUClass::tlb_fill	Richard Henderson	1	-13/+26
2019-04-18	target: Simplify how the TARGET_cpu_list() print	Markus Armbruster	1	-3/+4
2019-02-28	target/xtensa: reorganize register handling in translators	Max Filippov	1	-0/+15
2019-02-18	target/xtensa: allow multiple names for single opcode	Max Filippov	1	-3/+13
2019-02-18	target/xtensa: don't require opcode table sorting	Max Filippov	1	-0/+42
2019-02-18	target/xtensa: move xtensa_finalize_config to xtensa_core_class_init	Max Filippov	1	-17/+19
2019-02-10	target/xtensa: don't specify windowed registers manually	Max Filippov	1	-0/+1
2019-01-24	target/xtensa: add qemu_cpu_kick to xtensa_runstall	Max Filippov	1	-1/+1
2019-01-13	target/xtensa: move non-HELPER functions to helper.c	Max Filippov	1	-3/+58
2019-01-13	target/xtensa: extract interrupt and exception helpers	Max Filippov	1	-127/+0
2019-01-13	target/xtensa: extract MMU helpers	Max Filippov	1	-487/+0
2018-10-01	target/xtensa: extract test for an illegal instruction	Max Filippov	1	-0/+6
2018-09-17	target/xtensa: convert to do_transaction_failed	Max Filippov	1	-7/+23
2018-08-19	target/xtensa: clean up gdbstub register handling	Max Filippov	1	-11/+1
2018-08-19	target/xtensa: fix gdbstub register counts	Max Filippov	1	-1/+3
2018-07-02	hw/xtensa: Use the IEC binary prefix definitions	Philippe Mathieu-Daudé	1	-2/+3
2018-03-16	target/xtensa: add linux-user support	Max Filippov	1	-0/+31
2018-03-13	target/xtensa: use correct number of registers in gdbstub	Max Filippov	1	-8/+20
2018-01-09	target/xtensa: use libisa for instruction decoding	Max Filippov	1	-0/+37
2017-10-27	xtensa: cleanup cpu type name composition	Igor Mammedov	1	-1/+1
2017-09-01	xtensa: replace cpu_xtensa_init() with cpu_generic_init()	Igor Mammedov	1	-22/+0
2017-03-09	target/xtensa: hold BQL for interrupt processing	Alex Bennée	1	-0/+1
2017-01-15	target/xtensa: implement RUNSTALL	Max Filippov	1	-0/+13
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-0/+730