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sparc
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Author
Files
Lines
2017-05-23
shutdown: Add source information to SHUTDOWN and RESET
Eric Blake
1
-1
/
+1
2017-03-09
sparc/sparc64: grab BQL before calling cpu_check_irqs
Alex Bennée
2
-0
/
+16
2017-03-02
target/sparc: Restore ldstub of odd asis
Richard Henderson
1
-2
/
+25
2017-02-24
cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmap
Alex Bennée
1
-3
/
+5
2017-02-21
monitor: Fix crashes when using HMP commands without CPU
Thomas Huth
1
-0
/
+4
2017-01-24
migration: extend VMStateInfo
Jianjun Duan
1
-2
/
+4
2017-01-18
target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs
Artyom Tarasenko
1
-0
/
+11
2017-01-18
target-sparc: store the UA2005 entries in sun4u format
Artyom Tarasenko
2
-8
/
+47
2017-01-18
target-sparc: implement UA2005 ASI_MMU (0x21)
Artyom Tarasenko
1
-0
/
+31
2017-01-18
target-sparc: add more registers to dump_mmu
Artyom Tarasenko
1
-0
/
+2
2017-01-18
target-sparc: implement auto-demapping for UA2005 CPUs
Artyom Tarasenko
1
-0
/
+22
2017-01-18
target-sparc: allow 256M sized pages
Artyom Tarasenko
1
-17
/
+1
2017-01-18
target-sparc: simplify ultrasparc_tsb_pointer
Artyom Tarasenko
1
-36
/
+15
2017-01-18
target-sparc: implement UA2005 TSB Pointers
Artyom Tarasenko
2
-22
/
+104
2017-01-18
target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs
Artyom Tarasenko
3
-36
/
+24
2017-01-18
target-sparc: replace the last tlb entry when no free entries left
Artyom Tarasenko
1
-2
/
+4
2017-01-18
target-sparc: ignore writes to UA2005 CPU mondo queue register
Artyom Tarasenko
1
-0
/
+1
2017-01-18
target-sparc: allow priveleged ASIs in hyperprivileged mode
Artyom Tarasenko
1
-14
/
+18
2017-01-18
target-sparc: use direct address translation in hyperprivileged mode
Artyom Tarasenko
2
-5
/
+4
2017-01-18
target-sparc: fix immediate UA2005 traps
Artyom Tarasenko
1
-1
/
+1
2017-01-18
target-sparc: implement UA2005 rdhpstate and wrhpstate instructions
Artyom Tarasenko
1
-2
/
+5
2017-01-18
target-sparc: implement UA2005 GL register
Artyom Tarasenko
6
-7
/
+58
2017-01-18
target-sparc: implement UA2005 hypervisor traps
Artyom Tarasenko
3
-5
/
+39
2017-01-18
target-sparc: hypervisor mode takes over nucleus mode
Artyom Tarasenko
2
-3
/
+7
2017-01-18
target-sparc: implement UltraSPARC-T1 Strand status ASR
Artyom Tarasenko
1
-0
/
+11
2017-01-18
target-sparc: implement UA2005 scratchpad registers
Artyom Tarasenko
3
-0
/
+26
2017-01-18
target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE
Artyom Tarasenko
1
-3
/
+2
2017-01-18
target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode
Artyom Tarasenko
1
-1
/
+2
2017-01-18
target-sparc: add UltraSPARC T1 TLB #defines
Artyom Tarasenko
1
-0
/
+4
2017-01-18
target-sparc: add UA2005 TTE bit #defines
Artyom Tarasenko
1
-0
/
+17
2017-01-18
target-sparc: use explicit mmu register pointers
Artyom Tarasenko
2
-12
/
+58
2017-01-18
target-sparc: store cpu super- and hypervisor flags in TB
Artyom Tarasenko
2
-5
/
+36
2017-01-18
target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode
Artyom Tarasenko
2
-2
/
+15
2017-01-13
cputlb: drop flush_global flag from tlb_flush
Alex Bennée
1
-6
/
+6
2017-01-13
qom/cpu: move tlb_flush to cpu_common_reset
Alex Bennée
2
-2
/
+4
2017-01-10
target-sparc: Use ctpop helper
Richard Henderson
3
-7
/
+1
2016-12-20
Move target-* CPU file into a target/ folder
Thomas Huth
21
-0
/
+13805