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2024-04-26target/sparc: Replace abi_ulong by uint32_t for TARGET_ABI32Philippe Mathieu-Daudé1-1/+1
2024-04-26target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h'Philippe Mathieu-Daudé2-23/+23
2024-04-25hw, target: Add ResetType argument to hold and exit phase methodsPeter Maydell1-2/+2
2024-04-12target/sparc: Use GET_ASI_CODE for ASI_KERNELTXT and ASI_USERTXTRichard Henderson3-22/+94
2024-03-18target/sparc/cpu: Improve the CPU help textThomas Huth1-2/+3
2024-03-12target/sparc: Prefer fast cpu_env() over slower CPU QOM cast macroPhilippe Mathieu-Daudé7-38/+18
2024-03-12target: Replace CPU_GET_CLASS(cpu -> obj) in cpu_reset_hold() handlerPhilippe Mathieu-Daudé1-3/+3
2024-03-05accel/tcg: Add tlb_fill_flags to CPUTLBEntryFullRichard Henderson1-1/+1
2024-02-21target/sparc: correct typosManos Pitsidianakis1-4/+4
2024-02-15target/sparc: implement asr17 feature for smpClément Chigot3-10/+20
2024-02-15target/sparc: Provide hint about CPUSPARCState::irq_manager memberPhilippe Mathieu-Daudé1-3/+2
2024-02-03target/sparc: Use TCG_COND_TSTEQ in gen_op_mulsccRichard Henderson1-2/+2
2024-02-03target/sparc: Remove FSR_FTT_NMASK, FSR_FTT_CEXC_NMASKRichard Henderson1-7/+0
2024-02-03target/sparc: Split fcc out of env->fsrRichard Henderson4-522/+198
2024-02-03target/sparc: Remove cpu_fsrRichard Henderson3-113/+114
2024-02-03target/sparc: Split cexc and ftt from env->fsrRichard Henderson4-38/+48
2024-02-03target/sparc: Merge check_ieee_exceptions with FPop helpersRichard Henderson3-129/+219
2024-02-03target/sparc: Clear cexc and ftt in do_check_ieee_exceptionsRichard Henderson2-16/+2
2024-02-03target/sparc: Split ver from env->fsrRichard Henderson3-16/+23
2024-02-03target/sparc: Introduce cpu_get_fsr, cpu_put_fsrRichard Henderson7-12/+70
2024-02-03target/sparc: Remove qt0, qt1 temporariesRichard Henderson3-8/+0
2024-02-03target/sparc: Use i128 for FdmulqRichard Henderson3-16/+9
2024-02-03target/sparc: Use i128 for FdTOq, FxTOqRichard Henderson3-10/+11
2024-02-03target/sparc: Use i128 for FsTOq, FiTOqRichard Henderson3-10/+11
2024-02-03target/sparc: Use i128 for FCMPq, FCMPEqRichard Henderson3-52/+41
2024-02-03target/sparc: Use i128 for FqTOd, FqTOxRichard Henderson3-9/+10
2024-02-03target/sparc: Use i128 for FqTOs, FqTOiRichard Henderson3-9/+10
2024-02-03target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVqRichard Henderson3-28/+26
2024-02-03target/sparc: Use i128 for FSQRTqRichard Henderson3-8/+32
2024-02-03target/sparc: Inline FNEG, FABSRichard Henderson3-72/+30
2024-02-03target/sparc: Introduce gen_{load,store}_fpr_QRichard Henderson1-6/+19
2024-02-03target/sparc: Remove gen_dest_fpr_FRichard Henderson1-11/+6
2024-02-03target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BFILLRichard Henderson1-16/+15
2024-02-03target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BCOPYRichard Henderson1-19/+26
2024-02-03include/exec: Change cpu_mmu_index argument to CPUStateRichard Henderson3-3/+3
2024-02-03include/exec: Implement cpu_mmu_index genericallyRichard Henderson2-7/+1
2024-02-03target/sparc: Populate CPUClass.mmu_indexRichard Henderson2-28/+35
2024-01-29include/qemu: Add TCGCPUOps typedef to typedefs.hRichard Henderson1-1/+1
2024-01-29target: Use vaddr in gen_intermediate_codeAnton Johansson1-1/+1
2024-01-08system/cpus: rename qemu_mutex_lock_iothread() to bql_lock()Stefan Hajnoczi3-14/+14
2024-01-05target/sparc: Simplify qemu_irq_ackClément Chigot2-2/+2
2023-12-29target/sparc: Constify VMState in machine.cRichard Henderson1-4/+4
2023-11-14target/sparc: Fix RETURNRichard Henderson1-1/+1
2023-11-07target: Move ArchCPUClass definition to 'cpu.h'Philippe Mathieu-Daudé2-20/+16
2023-11-07target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'Philippe Mathieu-Daudé2-3/+4
2023-11-07target: Unify QOM stylePhilippe Mathieu-Daudé2-4/+0
2023-11-05target/sparc: Check for invalid cond in gen_compare_regRichard Henderson1-19/+26
2023-11-05target/sparc: Implement UDIV inlineRichard Henderson2-14/+56
2023-11-05target/sparc: Implement UDIVX and SDIVX inlineRichard Henderson4-44/+97
2023-11-05target/sparc: Discard cpu_cond at the end of each insnRichard Henderson1-0/+27