| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2017-01-18 | target-sparc: implement UA2005 scratchpad registers | Artyom Tarasenko | 1 | -0/+1 |
| 2017-01-18 | target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode | Artyom Tarasenko | 1 | -1/+2 |
| 2017-01-18 | target-sparc: add UltraSPARC T1 TLB #defines | Artyom Tarasenko | 1 | -0/+4 |
| 2017-01-18 | target-sparc: add UA2005 TTE bit #defines | Artyom Tarasenko | 1 | -0/+17 |
| 2017-01-18 | target-sparc: use explicit mmu register pointers | Artyom Tarasenko | 1 | -0/+4 |
| 2017-01-18 | target-sparc: store cpu super- and hypervisor flags in TB | Artyom Tarasenko | 1 | -0/+17 |
| 2017-01-18 | target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode | Artyom Tarasenko | 1 | -0/+2 |
| 2017-01-13 | qom/cpu: move tlb_flush to cpu_common_reset | Alex Bennée | 1 | -0/+3 |
| 2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth | 1 | -0/+779 |
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index : riscv-gnu-toolchain/qemu.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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