index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target
/
riscv
Age
Commit message (
Expand
)
Author
Files
Lines
2021-03-22
target/riscv: Prevent lost illegal instruction exceptions
Georg Kotheimer
1
-178
/
+1
2021-03-22
target/riscv: Add proper two-stage lookup exception detection
Georg Kotheimer
3
-13
/
+13
2021-03-22
target/riscv: Fix read and write accesses to vsip and vsie
Georg Kotheimer
1
-34
/
+34
2021-03-22
target/riscv: Use background registers also for MSTATUS_MPV
Georg Kotheimer
1
-1
/
+1
2021-03-22
target/riscv: Make VSTIP and VSEIP read-only in hip
Georg Kotheimer
1
-3
/
+4
2021-03-22
target/riscv: Adjust privilege level for HLV(X)/HSV instructions
Georg Kotheimer
1
-11
/
+14
2021-03-22
target/riscv: flush TLB pages if PMP permission has been changed
Jim Shu
1
-0
/
+4
2021-03-22
target/riscv: add log of PMP permission checking
Jim Shu
1
-0
/
+12
2021-03-22
target/riscv: propagate PMP permission to TLB page
Jim Shu
3
-43
/
+125
2021-03-22
target/riscv: fix vs() to return proper error code
Frank Chang
1
-1
/
+1
2021-03-11
Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.0-pul...
Peter Maydell
1
-1
/
+1
2021-03-10
semihosting: Move include/hw/semihosting/ -> include/semihosting/
Philippe Mathieu-Daudé
1
-1
/
+1
2021-03-09
Various spelling fixes
Michael Tokarev
1
-1
/
+1
2021-03-04
target-riscv: support QMP dump-guest-memory
Yifei Jiang
5
-0
/
+210
2021-03-04
target/riscv: Declare csr_ops[] with a known size
Bin Meng
1
-1
/
+1
2021-02-05
cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
Claudio Fontana
1
-7
/
+16
2021-02-05
cpu: move do_unaligned_access to tcg_ops
Claudio Fontana
1
-1
/
+1
2021-02-05
cpu: move cc->transaction_failed to tcg_ops
Claudio Fontana
2
-2
/
+2
2021-02-05
cpu: move cc->do_interrupt to tcg_ops
Claudio Fontana
1
-1
/
+1
2021-02-05
cpu: Move tlb_fill to tcg_ops
Eduardo Habkost
1
-1
/
+1
2021-02-05
cpu: Move cpu_exec_* to tcg_ops
Eduardo Habkost
1
-1
/
+1
2021-02-05
cpu: Move synchronize_from_tb() to tcg_ops
Eduardo Habkost
1
-1
/
+1
2021-02-05
target/riscv: remove CONFIG_TCG, as it is always TCG
Claudio Fontana
1
-2
/
+1
2021-02-05
cpu: Introduce TCGCpuOperations struct
Eduardo Habkost
1
-1
/
+1
2021-01-18
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-misc-1801...
Peter Maydell
4
-1
/
+58
2021-01-18
riscv: Add semihosting support
Keith Packard
4
-1
/
+58
2021-01-16
target/riscv: Generate the GDB XML file for CSR registers dynamically
Bin Meng
3
-264
/
+58
2021-01-16
target/riscv: Add CSR name in the CSR function table
Bin Meng
2
-84
/
+249
2021-01-16
target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
Bin Meng
2
-9
/
+9
2021-01-16
target/riscv/pmp: Raise exception if no PMP entry is configured
Atish Patra
3
-2
/
+8
2021-01-16
gdb: riscv: Add target description
Sylvain Pelissier
1
-0
/
+13
2021-01-07
tcg: Make tb arg to synchronize_from_tb const
Richard Henderson
1
-1
/
+2
2020-12-17
target/riscv: cpu: Set XLEN independently from target
Alistair Francis
1
-9
/
+16
2020-12-17
target/riscv: csr: Remove compile time XLEN checks
Alistair Francis
2
-88
/
+92
2020-12-17
target/riscv: cpu_helper: Remove compile time XLEN checks
Alistair Francis
1
-5
/
+7
2020-12-17
target/riscv: cpu: Remove compile time XLEN checks
Alistair Francis
1
-9
/
+10
2020-12-17
target/riscv: Specify the XLEN for CPUs
Alistair Francis
1
-10
/
+23
2020-12-17
target/riscv: Add a riscv_cpu_is_32bit() helper function
Alistair Francis
2
-0
/
+11
2020-12-17
target/riscv: fpu_helper: Match function defs in HELPER macros
Alistair Francis
2
-24
/
+8
2020-12-17
target/riscv: Add a TYPE_RISCV_CPU_BASE CPU
Alistair Francis
1
-0
/
+6
2020-12-17
target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
Alex Richardson
1
-2
/
+2
2020-12-17
target/riscv: Fix the bug of HLVX/HLV/HSV
Yifei Jiang
1
-1
/
+2
2020-11-13
hmp: Pass monitor to mon_get_cpu_env()
Kevin Wolf
1
-1
/
+1
2020-11-09
target/riscv: Split the Hypervisor execute load helpers
Alistair Francis
3
-42
/
+17
2020-11-09
target/riscv: Remove the hyp load and store functions
Alistair Francis
5
-166
/
+59
2020-11-09
target/riscv: Remove the HS_TWO_STAGE flag
Alistair Francis
4
-51
/
+25
2020-11-09
target/riscv: Set the virtualised MMU mode when doing hyp accesses
Alistair Francis
1
-13
/
+17
2020-11-09
target/riscv: Add a virtualised MMU Mode
Alistair Francis
3
-3
/
+14
2020-11-03
target/riscv/csr.c : add space before the open parenthesis '('
Xinhao Zhang
1
-1
/
+1
2020-11-03
target/riscv: Add V extension state description
Yifei Jiang
1
-0
/
+25
[next]