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| author | Claudio Fontana <cfontana@suse.de> | 2021-02-04 17:39:10 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-02-05 10:24:14 -1000 |
| commit | 6a3d2e7c0654c3fb2d3368d05363d0635e8bb8ff (patch) | |
| tree | 852544a19259ec1d208df3d7b33bf5891de1fda7 /target/riscv | |
| parent | e9e51b7154404efc9af8735ab87c658a9c434cfd (diff) | |
| download | qemu-6a3d2e7c0654c3fb2d3368d05363d0635e8bb8ff.zip qemu-6a3d2e7c0654c3fb2d3368d05363d0635e8bb8ff.tar.gz qemu-6a3d2e7c0654c3fb2d3368d05363d0635e8bb8ff.tar.bz2 | |
target/riscv: remove CONFIG_TCG, as it is always TCG
for now only TCG is allowed as an accelerator for riscv,
so remove the CONFIG_TCG use.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210204163931.7358-3-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 567f679..60d0b43 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -617,10 +617,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) #endif cc->gdb_arch_name = riscv_gdb_arch_name; cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; -#ifdef CONFIG_TCG cc->tcg_ops.initialize = riscv_translate_init; cc->tlb_fill = riscv_cpu_tlb_fill; -#endif + device_class_set_props(dc, riscv_cpu_properties); } |