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2019-03-13target/riscv: Convert quadrant 0 of RVXC insns to decodetreeBastian Koppelmann4-38/+154
2019-03-13target/riscv: Convert RV priv insns to decodetreeBastian Koppelmann3-56/+126
2019-03-13target/riscv: Convert RV64D insns to decodetreeBastian Koppelmann3-600/+91
2019-03-13target/riscv: Convert RV32D insns to decodetreeBastian Koppelmann3-0/+389
2019-03-13target/riscv: Convert RV64F insns to decodetreeBastian Koppelmann2-0/+66
2019-03-13target/riscv: Convert RV32F insns to decodetreeBastian Koppelmann3-0/+415
2019-03-13target/riscv: Convert RV64A insns to decodetreeBastian Koppelmann3-144/+71
2019-03-13target/riscv: Convert RV32A insns to decodetreeBastian Koppelmann3-0/+178
2019-03-13target/riscv: Convert RVXM insns to decodetreeBastian Koppelmann4-9/+137
2019-03-13target/riscv: Convert RVXI csr insns to decodetreeBastian Koppelmann3-42/+88
2019-03-13target/riscv: Convert RVXI fence insns to decodetreeBastian Koppelmann3-12/+21
2019-03-13target/riscv: Convert RVXI arithmetic insns to decodetreeBastian Koppelmann4-9/+206
2019-03-13target/riscv: Convert RV64I load/store insns to decodetreeBastian Koppelmann4-10/+50
2019-03-13target/riscv: Convert RV32I load/store insns to decodetreeBastian Koppelmann2-0/+58
2019-03-13target/riscv: Convert RVXI branch insns to decodetreeBastian Koppelmann3-11/+69
2019-03-13target/riscv: Activate decodetree and implemnt LUI & AUIPCBastian Koppelmann4-14/+92
2019-02-11target/riscv: fix counter-enable checks in ctr()Xi Wang1-3/+9
2019-02-11RISC-V: Add misa runtime write supportMichael Clark4-3/+68
2019-02-11RISC-V: Add misa.MAFD checks to translateMichael Clark1-0/+158
2019-02-11RISC-V: Add misa to DisasContextMichael Clark1-35/+40
2019-02-11RISC-V: Add priv_ver to DisasContextAlistair Francis1-2/+5
2019-02-11RISC-V: Use riscv prefix consistently on cpu helpersMichael Clark5-37/+36
2019-02-11RISC-V: Implement mstatus.TSR/TW/TVMMichael Clark2-8/+34
2019-02-11RISC-V: Mark mstatus.fs dirtyRichard Henderson2-13/+39
2019-02-11RISC-V: Split out mstatus_fs from tb_flagsRichard Henderson2-8/+8
2019-01-09RISC-V: Implement existential predicates for CSRsMichael Clark4-79/+105
2019-01-09RISC-V: Implement atomic mip/sip CSR updatesMichael Clark1-28/+28
2019-01-08RISC-V: Implement modular CSR helper interfaceMichael Clark6-606/+904
2019-01-03Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-3.2-part1'...Peter Maydell3-11/+13
2018-12-20riscv/cpu: use device_class_set_parent_realizeMao Zhongyi1-2/+2
2018-12-20target/riscv/pmp.c: Fix pmp_decode_napot()Anup Patel1-1/+1
2018-12-20RISC-V: Add hartid and \n to interrupt loggingMichael Clark1-8/+10
2018-12-20Clean up includesMarkus Armbruster1-1/+0
2018-11-13RISC-V: Respect fences for user-only emulatorsPalmer Dabbelt1-2/+0
2018-11-13target/riscv: Fix sfence.vm/a both available in any priv versionBastian Koppelmann1-5/+13
2018-11-13target/riscv: Fix FCLASS_D being treated as RV64 onlyBastian Koppelmann1-1/+3
2018-10-30target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64Dayeol Lee1-1/+1
2018-10-17RISC-V: Update CSR and interrupt definitionsMichael Clark3-321/+370
2018-10-17RISC-V: Move non-ops from op_helper to cpu_helperMichael Clark3-36/+35
2018-10-17RISC-V: Allow setting and clearing multiple irqsMichael Clark2-18/+28
2018-09-05riscv: remove define cpu_init()Igor Mammedov1-1/+0
2018-09-05target/riscv: call gen_goto_tb on DISAS_TOO_MANYEmilio G. Cota1-6/+1
2018-09-05target/riscv: optimize indirect branchesEmilio G. Cota1-1/+1
2018-09-05target/riscv: optimize cross-page direct jumps in softmmuEmilio G. Cota1-1/+1
2018-09-04RISC-V: Simplify riscv_cpu_local_irqs_pendingMichael Clark1-22/+12
2018-09-04RISC-V: Improve page table walker spec complianceMichael Clark2-21/+45
2018-09-04RISC-V: Update address bits to support sv39 and sv48Michael Clark1-4/+4
2018-06-08RISC-V: Add trailing '\n' to qemu_log() callsPhilippe Mathieu-Daudé1-2/+4
2018-06-01tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson1-10/+10
2018-05-31Make address_space_translate{, _cached}() take a MemTxAttrs argumentPeter Maydell1-1/+1
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