diff options
| author | Xi Wang <xi.wang@gmail.com> | 2019-01-26 15:02:56 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-02-11 15:56:22 -0800 |
| commit | ff9f31d9a0d45da83f34207b7ccace850cfc465b (patch) | |
| tree | b7534aab035d6dc28eac82d16325b8c6f484db19 /target/riscv | |
| parent | 7d04ac38959f8115f2a029d81db1c8aac179aa95 (diff) | |
| download | qemu-ff9f31d9a0d45da83f34207b7ccace850cfc465b.zip qemu-ff9f31d9a0d45da83f34207b7ccace850cfc465b.tar.gz qemu-ff9f31d9a0d45da83f34207b7ccace850cfc465b.tar.bz2 | |
target/riscv: fix counter-enable checks in ctr()
Access to a counter in U-mode is permitted only if the corresponding
bit is set in both mcounteren and scounteren. The current code
ignores mcounteren and checks scounteren only for U-mode access.
Signed-off-by: Xi Wang <xi.wang@gmail.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/csr.c | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e72fcf1..960d2b0 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -56,9 +56,15 @@ static int fs(CPURISCVState *env, int csrno) static int ctr(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) - target_ulong ctr_en = env->priv == PRV_U ? env->scounteren : - env->priv == PRV_S ? env->mcounteren : -1U; - if (!(ctr_en & (1 << (csrno & 31)))) { + uint32_t ctr_en = ~0u; + + if (env->priv < PRV_M) { + ctr_en &= env->mcounteren; + } + if (env->priv < PRV_S) { + ctr_en &= env->scounteren; + } + if (!(ctr_en & (1u << (csrno & 31)))) { return -1; } #endif |