| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2022-06-10 | target/riscv: add support for zmmul extension v0.1 | Weiwei Li | 3 | -6/+20 |
| 2022-05-24 | target/riscv: add zicsr/zifencei to isa_string | Hongren (Zenithal) Zheng | 1 | -0/+2 |
| 2022-05-24 | target/riscv: Set [m|s]tval for both illegal and virtual instruction traps | Anup Patel | 4 | -5/+23 |
| 2022-05-24 | target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode | Anup Patel | 1 | -2/+1 |
| 2022-05-24 | target/riscv: Fix csr number based privilege checking | Anup Patel | 1 | -2/+6 |
| 2022-05-24 | target/riscv: Fix typo of mimpid cpu option | Frank Chang | 3 | -7/+7 |
| 2022-05-24 | target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize | Weiwei Li | 1 | -12/+12 |
| 2022-05-24 | target/riscv: Move/refactor ISA extension checks | Tsukasa OI | 1 | -15/+16 |
| 2022-05-24 | target/riscv: FP extension requirements | Tsukasa OI | 1 | -0/+25 |
| 2022-05-24 | target/riscv: Change "G" expansion | Tsukasa OI | 1 | -2/+5 |
| 2022-05-24 | target/riscv: Disable "G" by default | Tsukasa OI | 1 | -1/+1 |
| 2022-05-24 | target/riscv: Fix coding style on "G" expansion | Tsukasa OI | 1 | -2/+2 |
| 2022-05-24 | target/riscv: Add short-isa-string option | Tsukasa OI | 2 | -1/+7 |
| 2022-05-24 | target/riscv: Move Zhinx* extensions on ISA string | Tsukasa OI | 1 | -2/+2 |
| 2022-05-24 | target/riscv: rvv: Fix early exit condition for whole register load/store | eopXD | 1 | -27/+31 |
| 2022-05-24 | target/riscv: Fix VS mode hypervisor CSR access | Dylan Reid | 1 | -5/+5 |
| 2022-05-11 | Normalize header guard symbol definition | Markus Armbruster | 1 | -1/+1 |
| 2022-05-11 | Clean up ill-advised or unusual header guards | Markus Armbruster | 1 | -2/+2 |
| 2022-04-29 | target/riscv: add scalar crypto related extenstion strings to isa_string | Weiwei Li | 1 | -0/+13 |
| 2022-04-29 | target/riscv: Fix incorrect PTE merge in walk_pte | Ralf Ramsauer | 1 | -4/+7 |
| 2022-04-29 | target/riscv: rvk: expose zbk* and zk* properties | Weiwei Li | 1 | -0/+13 |
| 2022-04-29 | target/riscv: rvk: add CSR support for Zkr | Weiwei Li | 4 | -3/+103 |
| 2022-04-29 | target/riscv: rvk: add support for zksed/zksh extension | Weiwei Li | 4 | -0/+95 |
| 2022-04-29 | target/riscv: rvk: add support for sha512 related instructions for RV64 in zk... | Weiwei Li | 2 | -0/+58 |
| 2022-04-29 | target/riscv: rvk: add support for sha512 related instructions for RV32 in zk... | Weiwei Li | 2 | -0/+106 |
| 2022-04-29 | target/riscv: rvk: add support for sha256 related instructions in zknh extension | Weiwei Li | 2 | -0/+60 |
| 2022-04-29 | target/riscv: rvk: add support for zkne/zknd extension in RV64 | Weiwei Li | 4 | -0/+243 |
| 2022-04-29 | target/riscv: rvk: add support for zknd/zkne extension in RV32 | Weiwei Li | 6 | -1/+196 |
| 2022-04-29 | target/riscv: rvk: add support for zbkx extension | Weiwei Li | 4 | -0/+51 |
| 2022-04-29 | target/riscv: rvk: add support for zbkc extension | Weiwei Li | 2 | -3/+4 |
| 2022-04-29 | target/riscv: rvk: add support for zbkb extension | Weiwei Li | 5 | -28/+174 |
| 2022-04-29 | target/riscv: rvk: add cfg properties for zbk* and zk* | Weiwei Li | 2 | -0/+36 |
| 2022-04-29 | target/riscv: Support configuarable marchid, mvendorid, mipid CSR values | Frank Chang | 3 | -4/+47 |
| 2022-04-22 | target/riscv: cpu: Enable native debug feature | Bin Meng | 1 | -1/+1 |
| 2022-04-22 | target/riscv: machine: Add debug state description | Bin Meng | 1 | -0/+32 |
| 2022-04-22 | target/riscv: csr: Hook debug CSR read/write | Bin Meng | 4 | -0/+90 |
| 2022-04-22 | target/riscv: cpu: Add a config option for native debug | Bin Meng | 2 | -1/+8 |
| 2022-04-22 | target/riscv: debug: Implement debug related TCGCPUOps | Bin Meng | 3 | -0/+82 |
| 2022-04-22 | hw/intc: Make RISC-V ACLINT mtime MMIO register writable | Frank Chang | 2 | -6/+6 |
| 2022-04-22 | target/riscv/pmp: fix NAPOT range computation overflow | Nicolas Pitre | 1 | -11/+3 |
| 2022-04-22 | target/riscv: Use cpu_loop_exit_restore directly from mmu faults | Richard Henderson | 1 | -3/+3 |
| 2022-04-22 | target/riscv: fix start byte for vmv<nf>r.v when vstart != 0 | Weiwei Li | 1 | -3/+5 |
| 2022-04-22 | target/riscv: Add isa extenstion strings to the device tree | Atish Patra | 1 | -0/+60 |
| 2022-04-22 | target/riscv: misa to ISA string conversion fix | Tsukasa OI | 1 | -5/+5 |
| 2022-04-22 | target/riscv: optimize helper for vmv<nr>r.v | Weiwei Li | 3 | -33/+18 |
| 2022-04-22 | target/riscv: optimize condition assign for scale < 0 | Weiwei Li | 1 | -5/+3 |
| 2022-04-22 | target/riscv: Add initial support for the Sdtrig extension | Bin Meng | 4 | -0/+453 |
| 2022-04-22 | target/riscv: Allow software access to MIP SEIP | Alistair Francis | 3 | -3/+23 |
| 2022-04-22 | target/riscv: cpu: Fixup indentation | Alistair Francis | 1 | -10/+10 |
| 2022-04-22 | target/riscv: Enable privileged spec version 1.12 | Atish Patra | 2 | -3/+10 |
