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author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-04-23 10:34:59 +0800 |
---|---|---|
committer | Alistair Francis <alistair.francis@wdc.com> | 2022-04-29 10:47:45 +1000 |
commit | 5cc69ceb68c2bd00b3f62d7d65ec669a507b4f30 (patch) | |
tree | 804dcfc6673c5df6eadbab25a1f2887db410bf34 /target/riscv | |
parent | d8e81e3c18231e4dbab562f53e3e6cf7ad77735f (diff) | |
download | qemu-5cc69ceb68c2bd00b3f62d7d65ec669a507b4f30.zip qemu-5cc69ceb68c2bd00b3f62d7d65ec669a507b4f30.tar.gz qemu-5cc69ceb68c2bd00b3f62d7d65ec669a507b4f30.tar.bz2 |
target/riscv: rvk: add support for zbkc extension
- reuse partial instructions of zbc extension, update extension check for them
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220423023510.30794-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
-rw-r--r-- | target/riscv/insn32.decode | 3 | ||||
-rw-r--r-- | target/riscv/insn_trans/trans_rvb.c.inc | 4 |
2 files changed, 4 insertions, 3 deletions
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index fdceaf6..3a49aca 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -770,9 +770,10 @@ clzw 0110000 00000 ..... 001 ..... 0011011 @r2 ctzw 0110000 00001 ..... 001 ..... 0011011 @r2 cpopw 0110000 00010 ..... 001 ..... 0011011 @r2 -# *** RV32 Zbc Standard Extension *** +# *** RV32 Zbc/Zbkc Standard Extension *** clmul 0000101 .......... 001 ..... 0110011 @r clmulh 0000101 .......... 011 ..... 0110011 @r +# *** RV32 extra Zbc Standard Extension *** clmulr 0000101 .......... 010 ..... 0110011 @r # *** RV32 Zbs Standard Extension *** diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index f365775..5a57515 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -489,7 +489,7 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a) static bool trans_clmul(DisasContext *ctx, arg_clmul *a) { - REQUIRE_ZBC(ctx); + REQUIRE_EITHER_EXT(ctx, zbc, zbkc); return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul, NULL); } @@ -501,7 +501,7 @@ static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2) static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a) { - REQUIRE_ZBC(ctx); + REQUIRE_EITHER_EXT(ctx, zbc, zbkc); return gen_arith(ctx, a, EXT_NONE, gen_clmulh, NULL); } |