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2021-03-11Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.0-pul...Peter Maydell1-1/+1
2021-03-10semihosting: Move include/hw/semihosting/ -> include/semihosting/Philippe Mathieu-Daudé1-1/+1
2021-03-09Various spelling fixesMichael Tokarev1-1/+1
2021-03-04target-riscv: support QMP dump-guest-memoryYifei Jiang5-0/+210
2021-03-04target/riscv: Declare csr_ops[] with a known sizeBin Meng1-1/+1
2021-02-05cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana1-7/+16
2021-02-05cpu: move do_unaligned_access to tcg_opsClaudio Fontana1-1/+1
2021-02-05cpu: move cc->transaction_failed to tcg_opsClaudio Fontana2-2/+2
2021-02-05cpu: move cc->do_interrupt to tcg_opsClaudio Fontana1-1/+1
2021-02-05cpu: Move tlb_fill to tcg_opsEduardo Habkost1-1/+1
2021-02-05cpu: Move cpu_exec_* to tcg_opsEduardo Habkost1-1/+1
2021-02-05cpu: Move synchronize_from_tb() to tcg_opsEduardo Habkost1-1/+1
2021-02-05target/riscv: remove CONFIG_TCG, as it is always TCGClaudio Fontana1-2/+1
2021-02-05cpu: Introduce TCGCpuOperations structEduardo Habkost1-1/+1
2021-01-18Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-misc-1801...Peter Maydell4-1/+58
2021-01-18riscv: Add semihosting supportKeith Packard4-1/+58
2021-01-16target/riscv: Generate the GDB XML file for CSR registers dynamicallyBin Meng3-264/+58
2021-01-16target/riscv: Add CSR name in the CSR function tableBin Meng2-84/+249
2021-01-16target/riscv: Make csr_ops[CSR_TABLE_SIZE] externalBin Meng2-9/+9
2021-01-16target/riscv/pmp: Raise exception if no PMP entry is configuredAtish Patra3-2/+8
2021-01-16gdb: riscv: Add target descriptionSylvain Pelissier1-0/+13
2021-01-07tcg: Make tb arg to synchronize_from_tb constRichard Henderson1-1/+2
2020-12-17target/riscv: cpu: Set XLEN independently from targetAlistair Francis1-9/+16
2020-12-17target/riscv: csr: Remove compile time XLEN checksAlistair Francis2-88/+92
2020-12-17target/riscv: cpu_helper: Remove compile time XLEN checksAlistair Francis1-5/+7
2020-12-17target/riscv: cpu: Remove compile time XLEN checksAlistair Francis1-9/+10
2020-12-17target/riscv: Specify the XLEN for CPUsAlistair Francis1-10/+23
2020-12-17target/riscv: Add a riscv_cpu_is_32bit() helper functionAlistair Francis2-0/+11
2020-12-17target/riscv: fpu_helper: Match function defs in HELPER macrosAlistair Francis2-24/+8
2020-12-17target/riscv: Add a TYPE_RISCV_CPU_BASE CPUAlistair Francis1-0/+6
2020-12-17target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSRAlex Richardson1-2/+2
2020-12-17target/riscv: Fix the bug of HLVX/HLV/HSVYifei Jiang1-1/+2
2020-11-13hmp: Pass monitor to mon_get_cpu_env()Kevin Wolf1-1/+1
2020-11-09target/riscv: Split the Hypervisor execute load helpersAlistair Francis3-42/+17
2020-11-09target/riscv: Remove the hyp load and store functionsAlistair Francis5-166/+59
2020-11-09target/riscv: Remove the HS_TWO_STAGE flagAlistair Francis4-51/+25
2020-11-09target/riscv: Set the virtualised MMU mode when doing hyp accessesAlistair Francis1-13/+17
2020-11-09target/riscv: Add a virtualised MMU ModeAlistair Francis3-3/+14
2020-11-03target/riscv/csr.c : add space before the open parenthesis '('Xinhao Zhang1-1/+1
2020-11-03target/riscv: Add V extension state descriptionYifei Jiang1-0/+25
2020-11-03target/riscv: Add H extension state descriptionYifei Jiang1-0/+47
2020-11-03target/riscv: Add PMP state descriptionYifei Jiang3-11/+70
2020-11-03target/riscv: Add basic vmstate description of CPUYifei Jiang4-8/+81
2020-11-03target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unitYifei Jiang6-74/+41
2020-10-22target/riscv: raise exception to HS-mode at get_physical_addressYifei Jiang2-12/+34
2020-10-22target/riscv: Fix implementation of HLVX.WU instructionGeorg Kotheimer1-3/+3
2020-10-22target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interruptGeorg Kotheimer1-1/+3
2020-10-22target/riscv: Fix update of hstatus.SPVPGeorg Kotheimer1-1/+1
2020-10-22riscv: Convert interrupt logs to use qemu_log_mask()Alistair Francis2-2/+7
2020-10-05icount: rename functions to be consistent with the module nameClaudio Fontana1-2/+2
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